公开(公告)号：US08362588B2

公开(公告)日：2013-01-29

申请号：US13159147

申请日：2011-06-13

Applicant: Wen-Chieh Lee ,  Mou-Shiung Lin ,  Chien-Kang Chou ,  Yi-Cheng Liu ,  Chiu-Ming Chou ,  Jin-Yuan Lee

Inventor： Wen-Chieh Lee ,  Mou-Shiung Lin ,  Chien-Kang Chou ,  Yi-Cheng Liu ,  Chiu-Ming Chou ,  Jin-Yuan Lee

IPC: H01L29/00 ,  H01L23/52 ,  H01L23/48

CPC classification number: H01L23/3114 ,  H01L23/5227 ,  H01L23/525 ,  H01L24/05 ,  H01L24/10 ,  H01L24/13 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05624 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01009 ,  H01L2924/01011 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A method for fabricating a circuitry component includes providing a semiconductor substrate, a first coil over said semiconductor substrate, a passivation layer over said first coil; and depositing a second coil over said passivation layer and over said first coil. Said second coil may be deposited by forming a first metal layer over said passivation layer, forming a pattern defining layer over said first metal layer, a first opening in said pattern defining layer exposing said first metal layer, forming a second metal layer over said first metal layer exposed by said first opening, removing said pattern defining layer, and removing said first metal layer not under said second metal layer.

公开(公告)号：US20060004954A1

公开(公告)日：2006-01-05

申请号：US10880581

申请日：2004-07-01

Applicant: Hong-Gee Fang ,  Wen-Chieh Lee ,  Wei-Chieh Wu

Inventor： Hong-Gee Fang ,  Wen-Chieh Lee ,  Wei-Chieh Wu

IPC: G06F12/00

CPC classification number: G11C11/406 ,  G11C2211/4061

Abstract: A method for operating a memory device that comprises periodically generating a refresh request signal for performing a refresh operation, providing an access request signal for performing an access operation, performing the refresh operation if the refresh request signal occurs prior to the access request signal, and performing the access operation if the access request signal occurs prior to the refresh request signal.

Abstract translation: 一种用于操作存储器件的方法，包括周期性地产生用于执行刷新操作的刷新请求信号，提供用于执行访问操作的访问请求信号，如果刷新请求信号在访问请求信号之前发生，则执行刷新操作;以及 如果访问请求信号在刷新请求信号之前发生，则执行访问操作。

公开(公告)号：US6119080A

公开(公告)日：2000-09-12

申请号：US98667

申请日：1998-06-17

Applicant: Chi-Min Liu ,  Wen-Chieh Lee

Inventor： Chi-Min Liu ,  Wen-Chieh Lee

IPC: G06F17/14 ,  G10L19/02

CPC classification number: G06F17/147 ,  G10L19/0212

Abstract: A unified architecture for implementing the modified cosine transforms of various cosine modulated filter banks in audio compression standards comprises a permutation module and a transform computing module. A modified cosine transform is computed by a pre-permutation followed by a discrete cosine transform and an inverse modified cosine transform is computed by a discrete cosine transform followed by a post-permutation. The discrete cosine transform computed in the unified architecture is selected from the group of type-II, type-III and type-IV cosine transforms. The computation of an N point discrete cosine transform is decomposed into a permutation-add stage, a sub-transform stage for computing two N/2 point discrete cosine transforms selected from the same group, and a combination stage. The architecture results in good regularity and general applicability as well as reduces complexity.

Abstract translation: 用于实现音频压缩标准中的各种余弦调制滤波器组的修正余弦变换的统一架构包括置换模块和变换计算模块。 修正余弦变换通过预排列后跟离散余弦变换来计算，逆修正余弦变换通过后续排列后的离散余弦变换来计算。 在统一架构中计算的离散余弦变换选自II型，III型和IV型余弦变换。 N点离散余弦变换的计算被分解为置换加法阶段，用于计算从同一组中选择的两个N / 2点离散余弦变换的子变换级和组合级。 该架构具有良好的规律性和一般适用性，并降低了复杂性。

公开(公告)号：US08338969B2

公开(公告)日：2012-12-25

申请号：US12694564

申请日：2010-01-27

Applicant: I-An Chen ,  Wen-Chieh Lee

Inventor： I-An Chen ,  Wen-Chieh Lee

IPC: H01L23/48

CPC classification number: G06K19/07732 ,  G06F3/0679

Abstract: A serial advanced technology attachment (SATA) interface storage device. The SATA interface storage device can be used in cooperation with an electrical apparatus and comprises a substrate, a chip set, a SATA interface and a shell. The substrate has a first surface, a second surface corresponding to the first surface and a plurality of connectors between the first surface and the second surface. The chip set is disposed on the first surface. The SATA interface is disposed on the second surface and is electrically connected to the chip set via a part of the connectors so that the electrical apparatus may be electrically connected to the chip set via the SATA interface to access the chip set. The shell has a width and a thickness and defines a receiving space for receiving the substrate, the chip set and the SATA interface, where the width and the thickness conform to a micro-memory card standard.

Abstract translation: 串行高级技术附件（SATA）接口存储设备。 SATA接口存储设备可以与电气设备协同使用，并且包括基板，芯片组，SATA接口和外壳。 衬底具有第一表面，对应于第一表面的第二表面和在第一表面和第二表面之间的多个连接器。 芯片组设置在第一表面上。 SATA接口设置在第二表面上，并且经由一部分连接器电连接到芯片组，使得电气设备可以经由SATA接口电连接到芯片组以访问芯片组。 壳体具有宽度和厚度并且限定用于接收基板，芯片组和SATA接口的接收空间，其中宽度和厚度符合微存储卡标准。

公开(公告)号：US20090104769A1

公开(公告)日：2009-04-23

申请号：US12276419

申请日：2008-11-24

Applicant: Wen-Chieh Lee ,  Mou-Shiung Lin ,  Chien-Kang Chou ,  Yi-Cheng Liu ,  Chiu-Ming Chou ,  Jin-Yuan Lee

Inventor： Wen-Chieh Lee ,  Mou-Shiung Lin ,  Chien-Kang Chou ,  Yi-Cheng Liu ,  Chiu-Ming Chou ,  Jin-Yuan Lee

IPC: H01L21/283

CPC classification number: H01L23/3114 ,  H01L23/5227 ,  H01L23/525 ,  H01L24/05 ,  H01L24/10 ,  H01L24/13 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05624 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01009 ,  H01L2924/01011 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A method for fabricating a circuitry component includes providing a semiconductor substrate, a first coil over said semiconductor substrate, a passivation layer over said first coil; and depositing a second coil over said passivation layer and over said first coil. Said second coil may be deposited by forming a first metal layer over said passivation layer, forming a pattern defining layer over said first metal layer, a first opening in said pattern defining layer exposing said first metal layer, forming a second metal layer over said first metal layer exposed by said first opening, removing said pattern defining layer, and removing said first metal layer not under said second metal layer.

Abstract translation: 一种用于制造电路部件的方法包括提供半导体衬底，在所述半导体衬底上的第一线圈，在所述第一线圈上方的钝化层; 以及在所述钝化层上并在所述第一线圈上方沉积第二线圈。 所述第二线圈可以通过在所述钝化层上形成第一金属层而形成，在所述第一金属层上形成图案限定层，所述图案限定层中的第一开口暴露所述第一金属层，在所述第一金属层上形成第二金属层 由所述第一开口暴露的金属层，去除所述图案限定层，以及去除不在所述第二金属层下方的所述第一金属层。

公开(公告)号：US20070223274A1

公开(公告)日：2007-09-27

申请号：US11689760

申请日：2007-03-22

Applicant: Wen-Chieh Lee ,  Hsiang-Cheng Ho

Inventor： Wen-Chieh Lee ,  Hsiang-Cheng Ho

IPC: G11C14/00 ,  G11C7/10 ,  G11C11/34

CPC classification number: G11C5/066 ,  G11C5/14 ,  G11C11/005

Abstract: A complex memory chip is provided. The complex memory chip comprises a first pin, a second pin, a voltage generator, a flash memory, and a static random access memory (SRAM). The first pin is capable of transmitting a first voltage. The second pin is capable of transmitting a second voltage which is lower than the first voltage, so as to define a working voltage in association with the first voltage. The voltage generator generates a third voltage according to the first voltage, wherein the third voltage is greater than the first voltage. The flash memory and the SRAM operate under the working voltage. The flash memory erases data according to the third voltage.

Abstract translation: 提供复杂的存储器芯片。 复合存储器芯片包括第一引脚，第二引脚，电压发生器，闪存和静态随机存取存储器（SRAM）。 第一引脚能够发送第一电压。 第二引脚能够传输低于第一电压的第二电压，以便与第一电压相关联地定义工作电压。 电压发生器根据第一电压产生第三电压，其中第三电压大于第一电压。 闪存和SRAM在工作电压下工作。 闪存根据第三电压擦除数据。

公开(公告)号：US06633999B1

公开(公告)日：2003-10-14

申请号：US09475329

申请日：1999-12-30

Applicant: Wen-Chieh Lee

Inventor： Wen-Chieh Lee

IPC: G11B2100

CPC classification number: G06F11/1008 ,  G11C29/42

Abstract: An integrated circuit with on-chip resources to support the testing of data stored on the integrated circuit includes logic to compute a check code using data, or a combination of data and addresses, of a particular data set stored on the device. The check code produced using the stored version of the data set is compared with a test code produced using a correct version of the data set, to indicate whether the correct data set was successfully stored on the device. An on-chip store holds the code produced using the correct version, and an on-chip comparator is used to produce a flag indicating the success or failure of the test. During manufacturing of the device, the memory tester simply tests the flag.

Abstract translation: 具有用于支持对存储在集成电路上的数据的测试的片上资源的集成电路包括使用存储在设备上的特定数据集的数据或数据和地址的组合来计算校验码的逻辑。 将使用存储的数据集的版本产生的检查码与使用正确版本的数据集产生的测试代码进行比较，以指示正确的数据集是否已成功存储在设备上。 片上存储器保存使用正确版本产生的代码，并且片上比较器用于产生指示测试成功或失败的标志。 在设备制造过程中，记忆体测试仪只需测试标志。

公开(公告)号：US20110029708A1

公开(公告)日：2011-02-03

申请号：US12694564

申请日：2010-01-27

Applicant: I-An Chen ,  Wen-Chieh Lee

Inventor： I-An Chen ,  Wen-Chieh Lee

IPC: G06F13/12

CPC classification number: G06K19/07732 ,  G06F3/0679

Abstract: A serial advanced technology attachment (SATA) interface storage device. The SATA interface storage device can be used in cooperation with an electrical apparatus and comprises a substrate, a chip set, a SATA interface and a shell. The substrate has a first surface, a second surface corresponding to the first surface and a plurality of connectors between the first surface and the second surface. The chip set is disposed on the first surface. The SATA interface is disposed on the second surface and is electrically connected to the chip set via a part of the connectors so that the electrical apparatus may be electrically connected to the chip set via the SATA interface to access the chip set. The shell has a width and a thickness and defines a receiving space for receiving the substrate, the chip set and the SATA interface, where the width and the thickness conform to a micro-memory card standard.

Abstract translation: 串行高级技术附件（SATA）接口存储设备。 SATA接口存储设备可以与电气设备协同使用，并且包括基板，芯片组，SATA接口和外壳。 衬底具有第一表面，对应于第一表面的第二表面和在第一表面和第二表面之间的多个连接器。 芯片组设置在第一表面上。 SATA接口设置在第二表面上，并且经由一部分连接器电连接到芯片组，使得电气设备可以经由SATA接口电连接到芯片组以访问芯片组。 壳体具有宽度和厚度并且限定用于接收基板，芯片组和SATA接口的接收空间，其中宽度和厚度符合微存储卡标准。

公开(公告)号：US07457522B2

公开(公告)日：2008-11-25

申请号：US11030119

申请日：2005-01-07

Applicant: Eldon Liu ,  Wen-Chieh Lee

Inventor： Eldon Liu ,  Wen-Chieh Lee

IPC: H04N5/91 ,  H04N5/00

CPC classification number: H04N9/8227 ,  H04N5/85 ,  H04N9/8042

Abstract: A system and method of a DVD player for displaying multiple subtitles includes a loading platform for reading digital data of DVD storage media; an interface management platform of receiving end for transmitting a decoded message of a first subtitle set image to a comparison platform. The comparison platform is for checking whether control signal of the first subtitle set image from the loading platform exists in an accumulator register. If not, the digital data is analyzed and decoded through an analytic platform and a decoder platform according to an identifying code of data flow and the first subtitle set image control signal. Then a mixed digital video signal and a digital audio signal are outputted by an image construct platform and an output platform. The interface management platform of receiving end continuingly transmitting a decoded message of a second subtitle set image to the comparison platform and the comparison platform reads control signal of the second subtitle set image and compares it with the first subtitle set image retained temporarily in the accumulator register for decoding the subtitle set image contol signal inexistent in the accumulator register.

Abstract translation: 用于显示多个字幕的DVD播放器的系统和方法包括用于读取DVD存储介质的数字数据的加载平台; 用于将第一字幕集图像的解码消息发送到比较平台的接收端的接口管理平台。 比较平台用于检查来自加载平台的第一副标题集图像的控制信号是否存在于累加器寄存器中。 如果不是，则根据数据流的识别码和第一字幕集合图像控制信号，通过分析平台和解码器平台分析和解码数字数据。 然后，混合数字视频信号和数字音频信号由图像构建平台和输出平台输出。 接收端的接口管理平台将第二字幕集合图像的解码消息继续发送到比较平台，比较平台读取第二字幕集合图像的控制信号，并将其与暂时保留在累加器寄存器中的第一字幕集合图像进行比较 用于解码在累加器寄存器中不存在的字幕组图像轮廓信号。

公开(公告)号：US20080109215A1

公开(公告)日：2008-05-08

申请号：US11474277

申请日：2006-06-26

Applicant: Chi-min Liu ,  Wen-chieh Lee ,  Han-Wen Hsu

Inventor： Chi-min Liu ,  Wen-chieh Lee ,  Han-Wen Hsu

IPC: G10L19/00

CPC classification number: G10L21/038

Abstract: High frequency components of audio signals are reconstructed from the aspects of envelope and fine detail. The envelopes of the high frequency components are found through linear extrapolation of signals with frequencies lower than a cutoff frequency point. One method of reconstructing high frequency components is based on the linear extrapolation on the logarithm scale magnitudes of the transform coefficients of the audio signal in a frequency domain. The linear extrapolation is a linear approximation based on minimizing least squares of the logarithm scale magnitudes of the transform coefficients of the low frequency components. Another method is based on the linear extrapolation on the logarithm scale magnitudes of the envelope elements of the filterbank signals of the audio signal over a time segment. The linear extrapolation is a linear approximation based on minimizing least squares of the logarithm scale magnitudes of the envelope elements of the low frequency filterbank signals.

Abstract translation: 音频信号的高频分量从包络和细节的方面进行重构。 通过线性外推频率低于截止频率点的信号，发现高频分量的包络。 重构高频分量的一种方法是基于频域中音频信号的变换系数的对数标度幅度上的线性外推法。 线性外推是基于最小化低频分量的变换系数的对数标度幅度的最小二乘法的线性近似。 另一种方法是基于对时间段上的音频信号的滤波器组信号的包络元素的对数标度幅度的线性外推。 线性外推是基于最小化低频滤波器组信号的包络元件的对数标度幅度的最小二乘法的线性近似。