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24 条记录 (耗时 0.035 秒)

    Serial advanced technology attachment interface storage device
    7.
    发明授权
    Serial advanced technology attachment interface storage device 有权
    串行高级技术附件接口存储设备

    公开(公告)号：US08338969B2

    公开(公告)日：2012-12-25

    申请号：US12694564

    申请日：2010-01-27

    申请人： I-An Chen ,  Wen-Chieh Lee

    发明人： I-An Chen ,  Wen-Chieh Lee

    IPC分类号： H01L23/48

    CPC分类号： G06K19/07732 ,  G06F3/0679

    摘要： A serial advanced technology attachment (SATA) interface storage device. The SATA interface storage device can be used in cooperation with an electrical apparatus and comprises a substrate, a chip set, a SATA interface and a shell. The substrate has a first surface, a second surface corresponding to the first surface and a plurality of connectors between the first surface and the second surface. The chip set is disposed on the first surface. The SATA interface is disposed on the second surface and is electrically connected to the chip set via a part of the connectors so that the electrical apparatus may be electrically connected to the chip set via the SATA interface to access the chip set. The shell has a width and a thickness and defines a receiving space for receiving the substrate, the chip set and the SATA interface, where the width and the thickness conform to a micro-memory card standard.

    摘要翻译： 串行高级技术附件（SATA）接口存储设备。 SATA接口存储设备可以与电气设备协同使用，并且包括基板，芯片组，SATA接口和外壳。 衬底具有第一表面，对应于第一表面的第二表面和在第一表面和第二表面之间的多个连接器。 芯片组设置在第一表面上。 SATA接口设置在第二表面上，并且经由一部分连接器电连接到芯片组，使得电气设备可以经由SATA接口电连接到芯片组以访问芯片组。 壳体具有宽度和厚度并且限定用于接收基板，芯片组和SATA接口的接收空间，其中宽度和厚度符合微存储卡标准。

    Complex Memory Chip
    8.
    发明申请
    Complex Memory Chip 审中-公开
    复杂内存芯片

    公开(公告)号：US20070223274A1

    公开(公告)日：2007-09-27

    申请号：US11689760

    申请日：2007-03-22

    申请人： Wen-Chieh Lee ,  Hsiang-Cheng Ho

    发明人： Wen-Chieh Lee ,  Hsiang-Cheng Ho

    IPC分类号： G11C14/00 ,  G11C7/10 ,  G11C11/34

    CPC分类号： G11C5/066 ,  G11C5/14 ,  G11C11/005

    摘要： A complex memory chip is provided. The complex memory chip comprises a first pin, a second pin, a voltage generator, a flash memory, and a static random access memory (SRAM). The first pin is capable of transmitting a first voltage. The second pin is capable of transmitting a second voltage which is lower than the first voltage, so as to define a working voltage in association with the first voltage. The voltage generator generates a third voltage according to the first voltage, wherein the third voltage is greater than the first voltage. The flash memory and the SRAM operate under the working voltage. The flash memory erases data according to the third voltage.

    摘要翻译： 提供复杂的存储器芯片。 复合存储器芯片包括第一引脚，第二引脚，电压发生器，闪存和静态随机存取存储器（SRAM）。 第一引脚能够发送第一电压。 第二引脚能够传输低于第一电压的第二电压，以便与第一电压相关联地定义工作电压。 电压发生器根据第一电压产生第三电压，其中第三电压大于第一电压。 闪存和SRAM在工作电压下工作。 闪存根据第三电压擦除数据。

    Integrated circuit with on-chip data checking resources
    9.
    发明授权
    Integrated circuit with on-chip data checking resources 有权
    具有片上数据检测资源的集成电路

    公开(公告)号：US06633999B1

    公开(公告)日：2003-10-14

    申请号：US09475329

    申请日：1999-12-30

    申请人： Wen-Chieh Lee

    发明人： Wen-Chieh Lee

    IPC分类号： G11B2100

    CPC分类号： G06F11/1008 ,  G11C29/42

    摘要： An integrated circuit with on-chip resources to support the testing of data stored on the integrated circuit includes logic to compute a check code using data, or a combination of data and addresses, of a particular data set stored on the device. The check code produced using the stored version of the data set is compared with a test code produced using a correct version of the data set, to indicate whether the correct data set was successfully stored on the device. An on-chip store holds the code produced using the correct version, and an on-chip comparator is used to produce a flag indicating the success or failure of the test. During manufacturing of the device, the memory tester simply tests the flag.

    摘要翻译： 具有用于支持对存储在集成电路上的数据的测试的片上资源的集成电路包括使用存储在设备上的特定数据集的数据或数据和地址的组合来计算校验码的逻辑。 将使用存储的数据集的版本产生的检查码与使用正确版本的数据集产生的测试代码进行比较，以指示正确的数据集是否已成功存储在设备上。 片上存储器保存使用正确版本产生的代码，并且片上比较器用于产生指示测试成功或失败的标志。 在设备制造过程中，记忆体测试仪只需测试标志。

    System and method for refreshing random access memory cells
    10.
    发明授权
    System and method for refreshing random access memory cells 有权
    用于刷新随机存取存储单元的系统和方法

    公开(公告)号：US07433996B2

    公开(公告)日：2008-10-07

    申请号：US10880581

    申请日：2004-07-01

    申请人： Hong-Gee Fang ,  Wen-Chieh Lee ,  Wei-Chieh Wu

    发明人： Hong-Gee Fang ,  Wen-Chieh Lee ,  Wei-Chieh Wu

    IPC分类号： G06F12/00

    CPC分类号： G11C11/406 ,  G11C2211/4061

    摘要： A method for operating a memory device that comprises periodically generating a refresh request signal for performing a refresh operation, providing an access request signal for performing an access operation, performing the refresh operation if the refresh request signal occurs prior to the access request signal, and performing the access operation if the access request signal occurs prior to the refresh request signal.

    摘要翻译： 一种用于操作存储器件的方法，包括周期性地产生用于执行刷新操作的刷新请求信号，提供用于执行访问操作的访问请求信号，如果刷新请求信号在访问请求信号之前发生，则执行刷新操作;以及 如果访问请求信号在刷新请求信号之前发生，则执行访问操作。