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    Thin film transistor with electrodes resistant to oxidation and erosion
    1.
    发明授权
    Thin film transistor with electrodes resistant to oxidation and erosion 有权
    具有耐氧化和侵蚀的电极的薄膜晶体管

    公开(公告)号：US07800109B2

    公开(公告)日：2010-09-21

    申请号：US10907956

    申请日：2005-04-22

    申请人： Wen-Kuang Tsao ,  Hung-I Hsu ,  Hsiang-Hsien Chung ,  Min-Huang Chen

    发明人： Wen-Kuang Tsao ,  Hung-I Hsu ,  Hsiang-Hsien Chung ,  Min-Huang Chen

    IPC分类号： H01L29/76

    CPC分类号： H01L29/4908

    摘要： A thin film transistor including a gate, a gate insulating layer, a semiconductor layer, a source electrode and a drain electrode is provided. The gate is disposed over a substrate, wherein the gate comprises at least one layer of aluminum-yttrium alloy nitride. The gate insulating layer is formed over the substrate to cover the gate. The semiconductor layer is disposed over the gate insulating layer above the gate. The source electrode and the drain electrode are disposed over the semiconductor layer.

    摘要翻译： 提供了包括栅极，栅极绝缘层，半导体层，源极和漏极的薄膜晶体管。 栅极设置在衬底上，其中栅极包括至少一层铝 - 钇合金氮化物。 栅极绝缘层形成在衬底上以覆盖栅极。 半导体层设置在栅极上方的栅绝缘层上。 源电极和漏极设置在半导体层上。

    Thin film transistor and method of forming the same
    2.
    发明授权
    Thin film transistor and method of forming the same 有权
    薄膜晶体管及其形成方法

    公开(公告)号：US07408190B2

    公开(公告)日：2008-08-05

    申请号：US11160660

    申请日：2005-07-05

    申请人： Wen-Kuang Tsao ,  Hung-I Hsu

    发明人： Wen-Kuang Tsao ,  Hung-I Hsu

    IPC分类号： H01L29/04 ,  H01L29/10 ,  H01L31/20 ,  H01L31/036 ,  H01L31/0376

    CPC分类号： H01L29/4908 ,  H01L29/458

    摘要： A thin film transistor including a gate, a gate insulating layer, a semiconductor layer and a source/drain is provided. The gate is disposed over a substrate, wherein the gate comprises at least one molybdenum-niobium alloy nitride layer. The gate insulating layer is formed over the substrate to cover the gate. The semiconductor layer is disposed over the gate insulating layer above the gate. The source/drain is disposed over the semiconductor layer.

    摘要翻译： 提供了包括栅极，栅极绝缘层，半导体层和源极/漏极的薄膜晶体管。 栅极设置在衬底上，其中栅极包括至少一个钼 - 铌合金氮化物层。 栅极绝缘层形成在衬底上以覆盖栅极。 半导体层设置在栅极上方的栅绝缘层上。 源极/漏极设置在半导体层上。

    [THIN FILM TRANSISTOR AND FABRICATING METHOD THEREOF]
    3.
    发明申请
    [THIN FILM TRANSISTOR AND FABRICATING METHOD THEREOF] 有权
    [薄膜晶体管及其制造方法]

    公开(公告)号：US20050006645A1

    公开(公告)日：2005-01-13

    申请号：US10605403

    申请日：2003-09-29

    申请人： Yu-Chou Lee ,  Wen-Kuang Tsao

    发明人： Yu-Chou Lee ,  Wen-Kuang Tsao

    IPC分类号： H01L21/336 ,  H01L29/49 ,  H01L29/786 ,  H01L29/04 ,  H01L31/036

    CPC分类号： H01L29/66765 ,  H01L29/4908 ,  H01L29/78669

    摘要： A method for fabricating a thin film transistor (TFT) is described. A MoNb gate is formed on a substrate, and an insulating layer is formed on the substrate covering the gate. A channel layer is formed on the insulating layer above the gate, and a source/drain is formed on the channel layer to constitute a TFT. Since the gate is constituted of a MoNb layer, the contact resistance thereof can be reduced.

    摘要翻译： 对薄膜晶体管（TFT）的制造方法进行说明。 在基板上形成MoNb栅极，在覆盖栅极的基板上形成绝缘层。 在栅极上方的绝缘层上形成沟道层，在沟道层上形成源极/漏极，构成TFT。 由于栅极由MoNb层构成，所以可以降低其接触电阻。

    Plasma sputtering target assembly and manufacturing method therefor
    4.
    发明申请
    Plasma sputtering target assembly and manufacturing method therefor 审中-公开
    等离子体溅射靶组件及其制造方法

    公开(公告)号：US20080121521A1

    公开(公告)日：2008-05-29

    申请号：US11504075

    申请日：2006-08-15

    申请人： Hsiang-Hsien Chung ,  Wen-Kuang Tsao ,  Hung-Yi Hsu ,  Chien-Yu Chen

    发明人： Hsiang-Hsien Chung ,  Wen-Kuang Tsao ,  Hung-Yi Hsu ,  Chien-Yu Chen

    IPC分类号： C23C14/00

    CPC分类号： C23C14/3407 ,  C23C14/54 ,  H01J37/3426 ,  H01J37/3491

    摘要： A plasma sputtering target assembly and a method therefor are provided. The sputtering target assembly includes a target, a bonding layer having a plurality of particles and having a first side bonded with the target and second side, and a backplate bonded with the second side of the bonding layer. The particles are being provided when the backplate is heated. Alternatively, a plurality of protrusions is formed on the backplate and the bonding layer is larger than or equal to the protrusions in altitude. Since the bonding layer has a composition and sputter yield of the part different from that of the target, in sputtering, the bonding layer is made exposed to plasma and thus an exceptional discharging phenomenon is caused when the target is struck through. By detecting the phenomenon, whether the target is almost over-sputtered may be forecasted and the backplate may be prevented from being struck through.

    摘要翻译： 提供等离子体溅射靶组件及其方法。 溅射靶组件包括靶，具有多个颗粒并具有与靶和第二侧接合的第一侧的接合层和与接合层的第二侧接合的背板。 当背板被加热时，颗粒被提供。 或者，在背板上形成多个突起，并且接合层大于或等于高度的突起。 由于接合层具有与靶不同的部分的组成和溅射产率，因此在溅射中，使接合层暴露于等离子体，因此当靶被穿过时会引起特殊的放电现象。 通过检测该现象，可以预测目标是否几乎过度喷溅，并且可以防止背板被击穿。

    Method of forming thin film transistor
    8.
    发明授权
    Method of forming thin film transistor 有权
    薄膜晶体管的形成方法

    公开(公告)号：US07807519B2

    公开(公告)日：2010-10-05

    申请号：US12146439

    申请日：2008-06-25

    申请人： Wen-Kuang Tsao ,  Hung-I Hsu

    发明人： Wen-Kuang Tsao ,  Hung-I Hsu

    IPC分类号： H01L21/336

    CPC分类号： H01L29/4908 ,  H01L29/458

    摘要： A thin film transistor including a gate, a gate insulating layer, a semiconductor layer and a source/drain is provided. The gate is disposed over a substrate and includes at least one molybdenum-niobium alloy nitride layer. The gate insulating layer is formed over the substrate to cover the gate. The semiconductor layer is disposed over the gate insulating layer above the gate. The source/drain is disposed over the semiconductor layer.

    摘要翻译： 提供了包括栅极，栅极绝缘层，半导体层和源极/漏极的薄膜晶体管。 栅极设置在衬底上并且包括至少一个钼 - 铌合金氮化物层。 栅极绝缘层形成在衬底上以覆盖栅极。 半导体层设置在栅极上方的栅绝缘层上。 源极/漏极设置在半导体层上。

    METHOD OF FORMING THIN FILM TRANSISTOR
    9.
    发明申请
    METHOD OF FORMING THIN FILM TRANSISTOR 有权
    形成薄膜晶体管的方法

    公开(公告)号：US20080261356A1

    公开(公告)日：2008-10-23

    申请号：US12146439

    申请日：2008-06-25

    申请人： Wen-Kuang Tsao ,  Hung-I Hsu

    发明人： Wen-Kuang Tsao ,  Hung-I Hsu

    IPC分类号： H01L21/336

    CPC分类号： H01L29/4908 ,  H01L29/458

    摘要： A thin film transistor including a gate, a gate insulating layer, a semiconductor layer and a source/drain is provided. The gate is disposed over a substrate and includes at least one molybdenum-niobium alloy nitride layer. The gate insulating layer is formed over the substrate to cover the gate. The semiconductor layer is disposed over the gate insulating layer above the gate. The source/drain is disposed over the semiconductor layer.

    摘要翻译： 提供了包括栅极，栅极绝缘层，半导体层和源极/漏极的薄膜晶体管。 栅极设置在衬底上并且包括至少一个钼 - 铌合金氮化物层。 栅极绝缘层形成在衬底上以覆盖栅极。 半导体层设置在栅极上方的栅绝缘层上。 源极/漏极设置在半导体层上。

    ANTI-STATIC SUBSTRATE
    10.
    发明申请
    ANTI-STATIC SUBSTRATE 审中-公开
    防静电基板

    公开(公告)号：US20070048530A1

    公开(公告)日：2007-03-01

    申请号：US11162079

    申请日：2005-08-29

    申请人： Wen-Kuang Tsao ,  Chien-Yu Chen

    发明人： Wen-Kuang Tsao ,  Chien-Yu Chen

    IPC分类号： B32B17/06 ,  B32B19/00

    CPC分类号： B32B7/02

    摘要： An anti-electrostatic discharge substrate adapted to eliminate electrostatic charges generated from friction between a carrier and the anti-electrostatic discharge substrate is provided. The anti-electrostatic discharge substrate includes a substrate having a front surface and a back surface; and a conductive layer on the back surface, wherein the electrostatic charges accumulated on the carrier are eliminated through the conductive layer when the substrate is in contact with the carrier.

    摘要翻译： 提供了适于消除由载体和抗静电放电基板之间的摩擦产生的静电电荷的抗静电放电基板。 防静电放电衬底包括具有前表面和后表面的衬底; 以及背面上的导电层，其中当衬底与载体接触时，通过导电层消除积聚在载体上的静电电荷。