摘要:
Air ventilation cooling systems are described for operation in a portable power device. Each air ventilation system comprises a cord stand in a structure that allows efficient heat dissipation generated from a power module. In a first aspect of the invention, a portable power device with natural convection for heat transfer is disclosed. In a second aspect of the invention, portable power devices with forced convection for heat transfer are disclosed. A portable power device in a natural convection mode comprises an output cord; and a stand, coupled to the output cord, for mounting a power module in a substantially vertical orientation, the stand having a base with a first vertical piece extending from the base to a first fin that is parallel to the base and having a second vertical piece extending from the base to a second fin that is parallel to the base, the power module plugging into the stand for creating a first gap along an edge of the first fin that is adjacent to the a first side of the power module and creating a second gap along an edge of the second fin that is adjacent to the second side of the power module, the stand allowing vertical heat dissipation generated by the power module with air flow vertically through the first and second gaps.
摘要:
A microcontroller including a streamlined pipeline processor provides a predictable time period for executing a set of instructions including branch instructions. The microcontroller has a program counter, branch stack and pipeline stages that can be loaded in a single cycle, and allows only the execution stage of the pipeline to alter the CPU state. Thus, the instructions in stages preceding the execution stage can be annulled, and the necessary registers can be updated in the first cycle upon determination of a branch instruction. In subsequent cycles, instructions in the branch routine will flow through the pipeline, one stage per cycle. Thus, a fixed period for responding to a branch instruction is provided. A fixed period for responding to an interrupt is also provided, as is a selectable interrupt schedule for predictable instruction execution in a multi-tasking operation.
摘要:
A method for fault detection in microcontroller program memory includes a new move instruction. An address of program instruction data is placed in a word register and a mode register. The new address points to a new instruction in a program memory. The program instruction data is read from the program memory into an instruction register and then transferred from the instruction register to the word register and the mode register. The contents of the word register and the mode register are then written to a data memory. With the program instruction data now available in the data memory, the new instruction can be tested for data integrity and validity using, for example, fault detection mechanisms or processes. A system for fault detection to check instructions or data in the program memory for data integrity and validity in a program memory also is disclosed.
摘要:
An extendable device for providing radiation occlusion and/or aero-thermal protection is disclosed. In various representative aspects, the present invention generally includes an extendable collar and a flexure configured to provide elastic properties (e.g., to facilitate stowage and/or deployment with respect to conformational disposition of the flexure). The flexure is coupled to a collar and is also coupled to the housing of an optical device.
摘要:
A high voltage NMOS switch is adjustable in order to optimize the switch for proper operation with different circuit configurations. A high voltage booster, included within the high voltage NMOS switch, enables the switch to reclaim the previously unused second half-cycle of a power source waveform signal, which thereby increases the speed of the NMOS switch by a factor of two. In addition, the high voltage NMOS switch provides added ramp rate flexibility by enabling a user to optimize the ramp rate of the high voltage NMOS switch for different circuit configurations.
摘要:
A support for a substrate processing chamber comprises a fluid circulating reservoir comprising a channel having serpentine convolutions. A fluid inlet supplies a heat transfer fluid to the fluid circulating reservoir and a fluid outlet discharges the heat transfer fluid. In one version, the channel is doubled over to turn back upon itself.
摘要:
A power supply having a control circuit for controlling an output of the power supply, and a voltage monitor circuit for detecting a voltage at a first location and providing the detected voltage to a second location in the control circuit independent of any difference in ground voltage between the first location and the second location. The control circuit is configured to control the output of the power supply in response to the detected voltage provided by the voltage monitor circuit.
摘要:
A single ended sensing scheme amplifies the logic state stored within a non-volatile memory circuit by relying upon three stages, a clamping circuit, a first operational amplifier and a second operational amplifier. The clamping circuit clamps the voltage at a voltage level with a small voltage swing between the logic states. The first stage and second stage operational amplifiers increase the clamped voltage level. A reference memory circuit ensures that the sensing scheme output is properly adjusted to compensate for voltage and temperature variations as well as noise injection from the power supply and ground.
摘要:
In one embodiment a chamber body enabling semiconductor processing equipment to be at least partially housed in the chamber body, the semiconductor processing equipment being configured to process a substrate using fluids is disclosed. The chamber body being comprised of a base material implemented to form the chamber body, the chamber body defined by at least a bottom surface and wall surfaces that are integrally connected to the bottom surface to enable capture of overflows of fluids during the processing of the substrate over the chamber body. Additionally, the base material is metallic. The chamber body also has a primer coat material disposed over and on the base material. The primer coat material has metallic constituents to define an integrated bond with the base material along with non-metallic constituents. The chamber body further includes a main coat material disposed over and on the primer coat material. The main coat material being defined from non-metallic constituents, the non-metallic constituents of the main coat material defining an integrated bond with the primer coat material. The main coat material defined to completely overlie all the metallic constituents of the primer coat.
摘要:
A system and method for efficiently processing instructions in a pipeline architecture for a microcontroller and maintaining a fixed instruction execution per clock cycle rate is disclosed. The pipeline comprises four stages: an instruction fetch stage, an operand fetch stage, an execution stage, and a write back stage. In a first embodiment, an entire clock cycle is dedicated to the instruction fetch stage to the instruction fetch stage to retrieve instruction data from non-volatile memory in a single clock cycle. In a second embodiment, the operand fetch stage preliminarily decodes the instruction data to determine tasks to be performed to allow the execution stage to perform its time-intensive calculations in a single clock cycle. Additionally, the operand fetch stage initiates the performance of tasks determined from the decoding of the instructions to minimize the time required to perform those tasks by the execution stage. In one embodiment, a read address is generated responsive to determining that a read operation is to be performed by the execution stage. In a third embodiment, a dual port data memory is employed to allow the execution stage and the write back stage to perform read and write operations concurrently, in a single clock cycle. Additional embodiments are disclosed for addressing circumstances in which one stage modifies the data address pointer required by another stage or one stage writes to an data memory location required for a read operation by a previous stage. Thus, a one instruction per clock cycle rate is achieved and maintained.