Air ventilation cooling systems for a portable device
    1.
    发明申请
    Air ventilation cooling systems for a portable device 失效
    便携式设备的空气通风冷却系统

    公开(公告)号:US20050231908A1

    公开(公告)日:2005-10-20

    申请号:US10824883

    申请日:2004-04-14

    IPC分类号: H01M8/04 H05K5/00 H05K7/20

    CPC分类号: H01M8/04014

    摘要: Air ventilation cooling systems are described for operation in a portable power device. Each air ventilation system comprises a cord stand in a structure that allows efficient heat dissipation generated from a power module. In a first aspect of the invention, a portable power device with natural convection for heat transfer is disclosed. In a second aspect of the invention, portable power devices with forced convection for heat transfer are disclosed. A portable power device in a natural convection mode comprises an output cord; and a stand, coupled to the output cord, for mounting a power module in a substantially vertical orientation, the stand having a base with a first vertical piece extending from the base to a first fin that is parallel to the base and having a second vertical piece extending from the base to a second fin that is parallel to the base, the power module plugging into the stand for creating a first gap along an edge of the first fin that is adjacent to the a first side of the power module and creating a second gap along an edge of the second fin that is adjacent to the second side of the power module, the stand allowing vertical heat dissipation generated by the power module with air flow vertically through the first and second gaps.

    摘要翻译: 空气通风冷却系统被描述为在便携式电力设备中操作。 每个空气通风系统包括一个能够从功率模块产生的高效散热的结构的电线架。 在本发明的第一方面,公开了一种具有用于传热的自然对流的便携式电力装置。 在本发明的第二方面中,公开了具有用于传热的强制对流的便携式电力装置。 自然对流模式的便携式电源装置包括输出线; 以及与所述输出线耦合的支架,用于将功率模块安装在基本上垂直的方向上,所述支架具有底座,所述基座具有从所述基座延伸到第一鳍片的第一垂直件,所述第一鳍片平行于所述基座并且具有第二垂直 从基座延伸到与基座平行的第二鳍片,功率模块插入支架,用于沿与第一鳍片的边缘相邻的功率模块的第一侧产生第一间隙,并且产生 第二间隙沿着第二鳍片的与功率模块的第二侧相邻的边缘,支架允许由功率模块产生的垂直散热,空气沿着第一和第二间隙垂直流动。

    Jitter free instruction execution
    2.
    发明授权
    Jitter free instruction execution 失效
    无抖动指令执行

    公开(公告)号:US6047351A

    公开(公告)日:2000-04-04

    申请号:US989365

    申请日:1997-12-12

    摘要: A microcontroller including a streamlined pipeline processor provides a predictable time period for executing a set of instructions including branch instructions. The microcontroller has a program counter, branch stack and pipeline stages that can be loaded in a single cycle, and allows only the execution stage of the pipeline to alter the CPU state. Thus, the instructions in stages preceding the execution stage can be annulled, and the necessary registers can be updated in the first cycle upon determination of a branch instruction. In subsequent cycles, instructions in the branch routine will flow through the pipeline, one stage per cycle. Thus, a fixed period for responding to a branch instruction is provided. A fixed period for responding to an interrupt is also provided, as is a selectable interrupt schedule for predictable instruction execution in a multi-tasking operation.

    摘要翻译: 包括精简流水线处理器的微控制器提供用于执行包括分支指令的一组指令的可预测时间段。 微控制器具有可以在单个周期中加载的程序计数器,分支堆栈和流水线级,并且只允许管道的执行级改变CPU状态。 因此,在执行阶段之前的阶段的指令可以被取消,并且在确定分支指令时可以在第一周期中更新必要的寄存器。 在随后的循环中,分支程序中的指令将流过管道,每个循环一个阶段。 因此,提供了用于响应分支指令的固定周期。 还提供了用于响应中断的固定周期,以及在多任务操作中可预测的指令执行的可选中断调度。

    System and method for fault detection in microcontroller program memory
    3.
    发明授权
    System and method for fault detection in microcontroller program memory 失效
    微控制器程序存储器中的故障检测系统和方法

    公开(公告)号:US5894549A

    公开(公告)日:1999-04-13

    申请号:US989935

    申请日:1997-12-12

    IPC分类号: G06F11/10 G11C7/00 G11C13/00

    CPC分类号: G06F11/1008

    摘要: A method for fault detection in microcontroller program memory includes a new move instruction. An address of program instruction data is placed in a word register and a mode register. The new address points to a new instruction in a program memory. The program instruction data is read from the program memory into an instruction register and then transferred from the instruction register to the word register and the mode register. The contents of the word register and the mode register are then written to a data memory. With the program instruction data now available in the data memory, the new instruction can be tested for data integrity and validity using, for example, fault detection mechanisms or processes. A system for fault detection to check instructions or data in the program memory for data integrity and validity in a program memory also is disclosed.

    摘要翻译: 微控制器程序存储器中的故障检测方法包括新的移位指令。 程序指令数据的地址被放置在字寄存器和模式寄存器中。 新地址指向程序存储器中的新指令。 程序指令数据从程序存储器读入指令寄存器,然后从指令寄存器传送到字寄存器和模式寄存器。 然后将字寄存器和模式寄存器的内容写入数据存储器。 利用数据存储器中现有的程序指令数据,可以使用例如故障检测机制或过程来测试新指令的数据完整性和有效性。 公开了一种用于在程序存储器中检查程序存储器中的数据完整性和有效性的指令或数据的故障检测系统。

    DEVICE AND METHOD FOR PROVIDING RADIATION OCCLUSION AND AERO-THERMAL PROTECTION
    4.
    发明申请
    DEVICE AND METHOD FOR PROVIDING RADIATION OCCLUSION AND AERO-THERMAL PROTECTION 有权
    用于提供辐射消融和空气保护的装置和方法

    公开(公告)号:US20100270430A1

    公开(公告)日:2010-10-28

    申请号:US11679324

    申请日:2007-02-27

    IPC分类号: G21F3/00 B23P11/00 B64C1/38

    摘要: An extendable device for providing radiation occlusion and/or aero-thermal protection is disclosed. In various representative aspects, the present invention generally includes an extendable collar and a flexure configured to provide elastic properties (e.g., to facilitate stowage and/or deployment with respect to conformational disposition of the flexure). The flexure is coupled to a collar and is also coupled to the housing of an optical device.

    摘要翻译: 公开了一种用于提供辐射阻挡和/或空气 - 热保护的可延伸装置。 在各种代表性方面,本发明通常包括可延伸的套环和挠曲件,其构造成提供弹性性能(例如,以便于相对于挠曲件的构造布置来进行存放和/或展开)。 挠曲件联接到轴环并且还联接到光学装置的壳体。

    High-voltage NMOS switch
    5.
    发明授权
    High-voltage NMOS switch 失效
    高电压NMOS开关设计

    公开(公告)号:US06188265B1

    公开(公告)日:2001-02-13

    申请号:US08989846

    申请日:1997-12-12

    IPC分类号: H03K1716

    摘要: A high voltage NMOS switch is adjustable in order to optimize the switch for proper operation with different circuit configurations. A high voltage booster, included within the high voltage NMOS switch, enables the switch to reclaim the previously unused second half-cycle of a power source waveform signal, which thereby increases the speed of the NMOS switch by a factor of two. In addition, the high voltage NMOS switch provides added ramp rate flexibility by enabling a user to optimize the ramp rate of the high voltage NMOS switch for different circuit configurations.

    摘要翻译: 高电压NMOS开关是可调节的,以便优化开关,以便不同的电路配置正常工作。 包括在高压NMOS开关内的高压升压器使得开关能够回收先前未使用的电源波形信号的第二半周期,从而将NMOS开关的速度提高了2倍。 此外,高电压NMOS开关通过使用户能够优化用于不同电路配置的高压NMOS开关的斜坡率来提供附加的斜坡率灵活性。

    Power supply with reliable voltage feedback control
    7.
    发明申请
    Power supply with reliable voltage feedback control 失效
    电源具有可靠的电压反馈控制

    公开(公告)号:US20060290204A1

    公开(公告)日:2006-12-28

    申请号:US11152847

    申请日:2005-06-14

    申请人: Wing Cheng

    发明人: Wing Cheng

    IPC分类号: H02J1/10

    CPC分类号: H02J1/10 Y10T307/50

    摘要: A power supply having a control circuit for controlling an output of the power supply, and a voltage monitor circuit for detecting a voltage at a first location and providing the detected voltage to a second location in the control circuit independent of any difference in ground voltage between the first location and the second location. The control circuit is configured to control the output of the power supply in response to the detected voltage provided by the voltage monitor circuit.

    摘要翻译: 一种具有用于控制电源输出的控制电路的电源和用于检测第一位置处的电压并将检测到的电压提供给控制电路中的第二位置的电压监视电路,而与地电压之间的任何差异无关, 第一个位置和第二个位置。 控制电路被配置为响应于由电压监视器电路提供的检测电压来控制电源的输出。

    High speed, noise immune, single ended sensing scheme for non-volatile
memories
    8.
    发明授权
    High speed, noise immune, single ended sensing scheme for non-volatile memories 失效
    用于非易失性存储器的高速,无噪声,单端感测方案

    公开(公告)号:US5949728A

    公开(公告)日:1999-09-07

    申请号:US989936

    申请日:1997-12-12

    IPC分类号: G11C7/06 G11C16/28 G11C7/00

    CPC分类号: G11C16/28 G11C7/067

    摘要: A single ended sensing scheme amplifies the logic state stored within a non-volatile memory circuit by relying upon three stages, a clamping circuit, a first operational amplifier and a second operational amplifier. The clamping circuit clamps the voltage at a voltage level with a small voltage swing between the logic states. The first stage and second stage operational amplifiers increase the clamped voltage level. A reference memory circuit ensures that the sensing scheme output is properly adjusted to compensate for voltage and temperature variations as well as noise injection from the power supply and ground.

    摘要翻译: 单端感测方案通过依靠三个阶段来放大存储在非易失性存储器电路内的逻辑状态,钳位电路,第一运算放大器和第二运算放大器。 钳位电路在逻辑状态之间以小的电压摆幅将电压钳位在电压电平。 第一级和第二级运算放大器增加了钳位电压电平。 参考存储器电路确保感测方案输出被适当地调整以补偿电压和温度变化以及来自电源和接地的噪声注入。

    Chemical resistant semiconductor processing chamber bodies
    9.
    发明申请
    Chemical resistant semiconductor processing chamber bodies 审中-公开
    耐化学腐蚀的半导体加工室体

    公开(公告)号:US20080038448A1

    公开(公告)日:2008-02-14

    申请号:US11731075

    申请日:2007-03-30

    IPC分类号: B05C11/00 B05D3/00

    CPC分类号: H01L21/67051 H01L21/6719

    摘要: In one embodiment a chamber body enabling semiconductor processing equipment to be at least partially housed in the chamber body, the semiconductor processing equipment being configured to process a substrate using fluids is disclosed. The chamber body being comprised of a base material implemented to form the chamber body, the chamber body defined by at least a bottom surface and wall surfaces that are integrally connected to the bottom surface to enable capture of overflows of fluids during the processing of the substrate over the chamber body. Additionally, the base material is metallic. The chamber body also has a primer coat material disposed over and on the base material. The primer coat material has metallic constituents to define an integrated bond with the base material along with non-metallic constituents. The chamber body further includes a main coat material disposed over and on the primer coat material. The main coat material being defined from non-metallic constituents, the non-metallic constituents of the main coat material defining an integrated bond with the primer coat material. The main coat material defined to completely overlie all the metallic constituents of the primer coat.

    摘要翻译: 在一个实施例中,公开了使半导体处理设备能够至少部分地容纳在室主体中的室主体,半导体处理设备被配置为使用流体处理衬底。 腔室主体包括被实施成形成腔室主体的基底材料,至少由底部表面限定的腔体主体和与底部表面一体连接的壁表面,以在衬底的处理期间捕获流体溢出物 在房间的身体。 另外,基材是金属的。 腔室主体还具有设置在基底材料上方的底漆涂层材料。 底涂层材料具有金属成分,以与非金属组分一起界定与基材的整体结合。 室主体还包括设置在底漆涂层材料上和之上的主涂层材料。 主涂层材料由非金属组分定义,主涂层材料的非金属组分限定与底漆涂层材料的整体结合。 主涂层材料被定义为完全覆盖底漆涂层的所有金属成分。

    Four stage pipeline processing for a microcontroller
    10.
    发明授权
    Four stage pipeline processing for a microcontroller 失效
    微控制器四级流水线处理

    公开(公告)号:US06353880B1

    公开(公告)日:2002-03-05

    申请号:US09121224

    申请日:1998-07-22

    IPC分类号: G06F930

    CPC分类号: G06F9/3834 G06F9/3867

    摘要: A system and method for efficiently processing instructions in a pipeline architecture for a microcontroller and maintaining a fixed instruction execution per clock cycle rate is disclosed. The pipeline comprises four stages: an instruction fetch stage, an operand fetch stage, an execution stage, and a write back stage. In a first embodiment, an entire clock cycle is dedicated to the instruction fetch stage to the instruction fetch stage to retrieve instruction data from non-volatile memory in a single clock cycle. In a second embodiment, the operand fetch stage preliminarily decodes the instruction data to determine tasks to be performed to allow the execution stage to perform its time-intensive calculations in a single clock cycle. Additionally, the operand fetch stage initiates the performance of tasks determined from the decoding of the instructions to minimize the time required to perform those tasks by the execution stage. In one embodiment, a read address is generated responsive to determining that a read operation is to be performed by the execution stage. In a third embodiment, a dual port data memory is employed to allow the execution stage and the write back stage to perform read and write operations concurrently, in a single clock cycle. Additional embodiments are disclosed for addressing circumstances in which one stage modifies the data address pointer required by another stage or one stage writes to an data memory location required for a read operation by a previous stage. Thus, a one instruction per clock cycle rate is achieved and maintained.

    摘要翻译: 公开了一种用于在微控制器的流水线架构中有效处理指令并维持每个时钟周期速率的固定指令执行的系统和方法。 流水线包括四个阶段:指令提取阶段,操作数获取阶段,执行阶段和回写阶段。 在第一实施例中,整个时钟周期专用于指令提取级,以在单个时钟周期内从非易失性存储器检索指令数据。 在第二实施例中,操作数获取阶段预先对指令数据进行解码以确定要执行的任务,以允许执行阶段在单个时钟周期内执行其时间密集的计算。 此外,操作数获取阶段启动从指令解码确定的任务的执行,以最小化执行阶段执行这些任务所需的时间。 在一个实施例中,响应于确定执行阶段执行读取操作而产生读取地址。 在第三实施例中,采用双端口数据存储器来允许执行级和写回级在单个时钟周期内同时执行读和写操作。 公开了另外的实施例,用于解决一个阶段修改另一个阶段所需的数据地址指针或一个阶段向前一阶段的读取操作所需的数据存储器位置写入的情况。 因此,实现并保持每个时钟周期速率的一个指令。