公开(公告)号：US09190323B2

公开(公告)日：2015-11-17

申请号：US13354070

申请日：2012-01-19

申请人： Xunyuan Zhang ,  Hoon Kim

发明人： Xunyuan Zhang ,  Hoon Kim

IPC分类号： H01L23/52 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L21/76885 ,  H01L21/76838 ,  H01L21/76849 ,  H01L21/76852 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices having copper interconnects and methods for their fabrication are provided. In one embodiment, a semiconductor device is fabricated with a copper interconnect on substrate such as an FEOL processed substrate. The method includes forming a copper layer on a substrate. The copper layer is formed from grains. The copper layer is modified such that the modified copper layer has an average grain size of larger than about 0.05 microns. In the method, the modified copper layer is etched to form a line along the substrate and a via extending upwards from the line.

摘要翻译： 提供了具有铜互连的半导体器件及其制造方法。 在一个实施例中，在诸如FEOL处理的衬底的衬底上用铜互连制造半导体器件。 该方法包括在基板上形成铜层。 铜层由晶粒形成。 铜层被改性，使得改性铜层的平均粒度大于约0.05微米。 在该方法中，蚀刻改性铜层以形成沿着衬底的线和从该线向上延伸的通孔。

公开(公告)号：US20130187273A1

公开(公告)日：2013-07-25

申请号：US13354070

申请日：2012-01-19

申请人： Xunyuan Zhang ,  Hoon Kim

发明人： Xunyuan Zhang ,  Hoon Kim

IPC分类号： H01L23/532 ,  H01L21/768

CPC分类号： H01L21/76885 ,  H01L21/76838 ,  H01L21/76849 ,  H01L21/76852 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices having copper interconnects and methods for their fabrication are provided. In one embodiment, a semiconductor device is fabricated with a copper interconnect on substrate such as an FEOL processed substrate. The method includes forming a copper layer on a substrate. The copper layer is formed from grains. The copper layer is modified such that the modified copper layer has an average grain size of larger than about 0.05 microns. In the method, the modified copper layer is etched to form a line along the substrate and a via extending upwards from the line.

摘要翻译： 提供了具有铜互连的半导体器件及其制造方法。 在一个实施例中，在诸如FEOL处理的衬底的衬底上用铜互连制造半导体器件。 该方法包括在基板上形成铜层。 铜层由晶粒形成。 铜层被改性，使得改性铜层的平均粒度大于约0.05微米。 在该方法中，蚀刻改性铜层以形成沿着衬底的线和从该线向上延伸的通孔。

公开(公告)号：US08431482B1

公开(公告)日：2013-04-30

申请号：US13362981

申请日：2012-01-31

申请人： Errol T. Ryan ,  Xunyuan Zhang

发明人： Errol T. Ryan ,  Xunyuan Zhang

IPC分类号： H01L21/4763

CPC分类号： H01L23/535 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76883 ,  H01L21/76886 ,  H01L2924/0002 ,  H01L2924/00

摘要： Integrated circuits, a process for recessing an embedded copper feature within a substrate, and a process for recessing an embedded copper interconnect within an interlayer dielectric substrate of an integrated circuit are provided. In an embodiment, a process for recessing an embedded copper feature, such as an embedded copper interconnect, within a substrate, such as an interlayer dielectric substrate, includes providing a substrate having an embedded copper feature disposed therein. The embedded copper feature has an exposed surface and the substrate has a substrate surface adjacent to the exposed surface of the embedded copper feature. The exposed surface of the embedded copper feature is nitrided to form a layer of copper nitride in the embedded copper feature. Copper nitride is selectively etched from the embedded copper feature to recess the embedded copper feature within the substrate.

摘要翻译： 提供集成电路，用于凹入衬底内的嵌入式铜特征的工艺，以及用于使集成电路的层间电介质衬底内的嵌入式铜互连凹陷的工艺。 在一个实施例中，在诸如层间电介质基板的衬底内嵌入诸如嵌入式铜互连的嵌入式铜特征的方法包括提供其中布置有嵌入式铜特征的衬底。 嵌入的铜特征具有暴露的表面，并且衬底具有与嵌入的铜特征的暴露表面相邻的衬底表面。 嵌入的铜特征的暴露表面被氮化以在嵌入的铜特征中形成一层氮化铜。 从嵌入的铜特征中选择性地蚀刻氮化铜以将嵌入的铜特征凹入到衬底内。

公开(公告)号：US20140024212A1

公开(公告)日：2014-01-23

申请号：US13554020

申请日：2012-07-20

申请人： Vivian W. Ryan ,  Xunyuan Zhang ,  Paul R. Besser

发明人： Vivian W. Ryan ,  Xunyuan Zhang ,  Paul R. Besser

IPC分类号： H01L21/768

CPC分类号： H01L21/76873 ,  H01L21/76846 ,  H01L21/76858 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming an interconnect structure includes forming a recess in a dielectric layer of a substrate. An adhesion barrier layer is formed to line the recess. A first stress level is present across a first interface between the adhesion barrier layer and the dielectric layer. A stress-reducing barrier layer is formed over the adhesion barrier layer. The stress-reducing barrier layer reduces the first stress level to provide a second stress level, less than the first stress level, across a second interface between the adhesion barrier layer, the stress-reducing barrier layer, and the dielectric layer. The recess is filled with a fill layer.

摘要翻译： 形成互连结构的方法包括在基板的电介质层中形成凹部。 形成粘合阻挡层以使凹部成线。 第一应力水平存在于粘合阻挡层和电介质层之间的第一界面上。 在粘合阻挡层上方形成有应力降低阻挡层。 所述减小应力的阻挡层减小所述第一应力水平以提供小于所述第一应力水平的第二应力水平，所述第二应力水平穿过所述粘合阻挡层，所述减小应力阻挡层和所述介电层之间的第二界面。 该凹部填充有填充层。

公开(公告)号：US20130309868A1

公开(公告)日：2013-11-21

申请号：US13476860

申请日：2012-05-21

申请人： Xiuyu Cai ,  Xunyuan Zhang ,  Ruilong Xie ,  Errol T. Ryan ,  John A. Iacoponi

发明人： Xiuyu Cai ,  Xunyuan Zhang ,  Ruilong Xie ,  Errol T. Ryan ,  John A. Iacoponi

IPC分类号： H01L21/311

CPC分类号： H01L21/311 ,  H01L21/3105 ,  H01L21/31116 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76828 ,  H01L21/76831 ,  H01L29/66545

摘要： Methods are provided for forming an integrated circuit. In an embodiment, the method includes forming a sacrificial mandrel overlying a base substrate. Sidewall spacers are formed adjacent sidewalls of the sacrificial mandrel. The sidewall spacers have a lower portion that is proximal to the base substrate, and the lower portion has a substantially perpendicular outer surface relative to the base substrate. The sidewall spacers also have an upper portion that is spaced from the base substrate. The upper portion has a sloped outer surface. A first dielectric layer is formed overlying the base substrate and is conformal to at least a portion of the upper portion of the sidewall spacers. The upper portion of the sidewall spacers is removed after forming the first dielectric layer to form a recess having a re-entrant profile in the first dielectric layer. The re-entrant profile of the recess is straightened.

摘要翻译： 为形成集成电路提供了方法。 在一个实施例中，该方法包括形成覆盖在基底衬底上的牺牲心轴。 侧壁间隔件形成在牺牲心轴的相邻侧壁处。 侧壁间隔件具有靠近基底基底的下部，并且下部具有相对于基底的基本垂直的外表面。 侧壁间隔物还具有与基底基板间隔开的上部。 上部具有倾斜的外表面。 第一电介质层形成在基底衬底上，并且与侧壁间隔物的上部的至少一部分共形。 在形成第一介电层之后去除侧壁间隔物的上部，以在第一介电层中形成具有凹入轮廓的凹部。 凹槽的重新设计简洁直观。

公开(公告)号：US20130309863A1

公开(公告)日：2013-11-21

申请号：US13476692

申请日：2012-05-21

申请人： Sean X. Lin ,  Ming He ,  Xunyuan Zhang ,  Larry Zhao

发明人： Sean X. Lin ,  Ming He ,  Xunyuan Zhang ,  Larry Zhao

IPC分类号： H01L21/768

CPC分类号： H01L21/76874 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76879

摘要： Disclosed herein are various methods of forming copper-based conductive structures on integrated circuit devices. In one example, the method includes forming a trench/via in a layer of insulating material, performing a deposition process to form an as-deposited copper-based seed layer above the layer of insulating material in the trench/via, wherein the copper-based seed layer has a first portion that is positioned above a bottom of the trench/via that is thicker than second portions of the copper seed layer that are positioned above sidewalls of the trench/via, performing an etching process on the as-deposited copper-based seed layer to substantially remove portions of the second portions of the as-deposited copper-based seed layer and performing an electroless deposition process to fill the trench/via with a copper-based material.

摘要翻译： 这里公开了在集成电路器件上形成铜基导电结构的各种方法。 在一个示例中，该方法包括在绝缘材料层中形成沟槽/通孔，执行沉积工艺以在沟槽/通孔中的绝缘材料层上形成沉积的基于铜的种子层，其中铜 - 基于晶种的层具有位于沟槽/通孔的底部之上的第一部分，其比位于沟槽/通孔侧壁上方的铜籽晶层的第二部分更厚，对沉积的铜进行蚀刻工艺 基本种子层，以基本上去除沉积的铜基种子层的第二部分的部分，并执行无电沉积工艺以用铜基材料填充沟槽/通孔。

公开(公告)号：US08586473B1

公开(公告)日：2013-11-19

申请号：US13533816

申请日：2012-06-26

申请人： Kunaljeet Tanwar ,  Xunyuan Zhang ,  Ming He

发明人： Kunaljeet Tanwar ,  Xunyuan Zhang ,  Ming He

IPC分类号： H01L21/44

CPC分类号： H01L21/76843 ,  H01L21/7684 ,  H01L21/76849 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes depositing a dielectric layer defining a plane. In the method, the dielectric layer is etched to form trenches. Then, a ruthenium-containing liner layer is deposited overlying the dielectric layer. The trenches are filled with copper-containing metal. The method includes recessing the copper-containing metal in each trench to form a space between the copper-containing metal and the plane. The space is filled with a capping layer. The layers are then planarized to at least the plane.

摘要翻译： 提供了制造集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括沉积限定平面的电介质层。 在该方法中，蚀刻介电层以形成沟槽。 然后，沉积覆盖在介电层上的含钌衬里层。 沟槽用含铜金属填充。 该方法包括在每个沟槽中凹入含铜金属，以在含铜金属和平面之间形成空间。 空间填充有覆盖层。 然后将这些层平坦化至少至该平面。

公开(公告)号：US20130244421A1

公开(公告)日：2013-09-19

申请号：US13422295

申请日：2012-03-16

申请人： Sean X. LIN ,  Ming HE ,  Xunyuan ZHANG ,  Larry ZHAO

发明人： Sean X. LIN ,  Ming HE ,  Xunyuan ZHANG ,  Larry ZHAO

IPC分类号： H01L21/768

CPC分类号： H01L21/76879 ,  H01L21/76861 ,  H01L21/76864 ,  H01L21/76865 ,  H01L21/76874 ,  H01L2924/0002

摘要： Disclosed herein are various methods of forming copper-based conductive structures on integrated circuit devices. In one example, the method includes the steps of forming a trench/via in a layer of insulating material, forming a copper-based seed layer above the layer of insulating material and in the trench/via, performing a heating process on the copper-based seed layer to increase an amount of the copper-based seed layer positioned proximate a bottom of the trench/via, performing an etching process on said copper-based seed layer and performing an electroless copper deposition process to fill the trench/via with a copper-based material.

摘要翻译： 这里公开了在集成电路器件上形成铜基导电结构的各种方法。 在一个示例中，该方法包括以下步骤：在绝缘材料层中形成沟槽/通孔，在绝缘材料层上方和沟槽/通孔中形成铜基种子层，在铜 - 以增加位于沟槽/通孔的底部附近的铜基种子层的量，对所述铜基种子层进行蚀刻工艺，并执行无电镀铜沉积工艺以填充沟槽/通孔 铜基材料。

公开(公告)号：US08791014B2

公开(公告)日：2014-07-29

申请号：US13422439

申请日：2012-03-16

申请人： Xunyuan Zhang ,  Hoon Kim ,  Chanro Park

发明人： Xunyuan Zhang ,  Hoon Kim ,  Chanro Park

IPC分类号： H01L21/768

CPC分类号： H01L21/76879 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/31144 ,  H01L21/32134 ,  H01L21/76805 ,  H01L21/76816

摘要： Disclosed herein are various methods of forming copper-based conductive structures on semiconductor devices, such as transistors. In one example, the method involves performing a first etching process through a patterned metal hard mask layer to define an opening in a layer of insulating material, performing a second etching process through the opening in the layer of insulating material that exposes a portion of an underlying copper-containing structure, performing a wet etching process to remove the patterned metal hard mask layer, performing a selective metal deposition process through the opening in the layer of insulating material to selectively form a metal region on the copper-containing structure and, after forming the metal region, forming a copper-containing structure in the opening above the metal region.

摘要翻译： 本文公开了在诸如晶体管的半导体器件上形成铜基导电结构的各种方法。 在一个示例中，该方法包括通过图案化的金属硬掩模层执行第一蚀刻工艺以限定绝缘材料层中的开口，通过绝缘材料层中的开口执行第二蚀刻工艺，该开口暴露一部分 下面的含铜结构，进行湿蚀刻处理以去除图案化的金属硬掩模层，通过绝缘材料层中的开口进行选择性金属沉积工艺，以选择性地在含铜结构上形成金属区域，之后 形成金属区域，在金属区域上方的开口中形成含铜结构体。

公开(公告)号：US08728931B2

公开(公告)日：2014-05-20

申请号：US13553977

申请日：2012-07-20

申请人： Vivian W. Ryan ,  Xunyuan Zhang ,  Paul R. Besser

发明人： Vivian W. Ryan ,  Xunyuan Zhang ,  Paul R. Besser

IPC分类号： H01L21/4763

CPC分类号： H01L23/49866 ,  H01L21/76846 ,  H01L21/76858 ,  H01L21/76873 ,  H01L21/76886 ,  H01L23/49827 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming an interconnect structure includes forming a recess in a dielectric layer of a substrate. An adhesion barrier layer is formed to line the recess. A first stress level is present across a first interface between the adhesion barrier layer and the dielectric layer. A stress-reducing barrier layer is formed over the adhesion barrier layer. The stress-reducing barrier layer reduces the first stress level to provide a second stress level, less than the first stress level, across a second interface between the adhesion barrier layer, the stress-reducing barrier layer, and the dielectric layer. The recess is filled with a fill layer.

摘要翻译： 形成互连结构的方法包括在基板的电介质层中形成凹部。 形成粘合阻挡层以使凹部成线。 第一应力水平存在于粘合阻挡层和电介质层之间的第一界面上。 在粘合阻挡层上方形成有应力降低阻挡层。 所述减小应力的阻挡层减小所述第一应力水平以提供小于所述第一应力水平的第二应力水平，所述第二应力水平穿过所述粘合阻挡层，所述减小应力阻挡层和所述介电层之间的第二界面。 该凹部填充有填充层。