公开(公告)号：US20080180185A1

公开(公告)日：2008-07-31

申请号：US11701303

申请日：2007-01-31

Applicant: Yongping Fan ,  Ian Young

Inventor： Yongping Fan ,  Ian Young

IPC: H03L5/00 ,  H03B5/12

CPC classification number: H03L5/00 ,  H03L7/099 ,  H03L2207/06

Abstract: Disclosed are circuits and methods to control the amplitude of a signal generated by a VCO.

Abstract translation: 公开了用于控制由VCO产生的信号的幅度的电路和方法。

公开(公告)号：US5548137A

公开(公告)日：1996-08-20

申请号：US207327

申请日：1994-03-07

Applicant: Yongping Fan ,  Jung Han ,  Arto V. Nurimikko ,  Robert L. Gunshor ,  Li He

Inventor： Yongping Fan ,  Jung Han ,  Arto V. Nurimikko ,  Robert L. Gunshor ,  Li He

IPC: H01L21/36 ,  H01L21/44 ,  H01L27/15 ,  H01L33/06 ,  H01L33/08 ,  H01L33/14 ,  H01L33/26 ,  H01L33/28 ,  H01L33/40 ,  H01S5/042 ,  H01S5/223 ,  H01S5/347 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC classification number: H01S5/347 ,  B82Y20/00 ,  H01L21/02395 ,  H01L21/024 ,  H01L21/02417 ,  H01L21/02469 ,  H01L21/02485 ,  H01L21/0251 ,  H01L21/02557 ,  H01L21/0256 ,  H01L21/02562 ,  H01L21/02568 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/44 ,  H01L33/06 ,  H01L33/08 ,  H01L33/14 ,  H01S5/0421 ,  H01L27/156 ,  H01L33/26 ,  H01L33/28 ,  H01L33/40 ,  H01S5/2231

Abstract: Group II-VI compound semiconductor light emitting devices which include at least one II-VI quantum well region of a well layer disposed between first and second barrier layers is disclosed. The quantum well region is sandwiched between first and second cladding layers of a II-VI semiconductor material. The first cladding layer is formed on and lattice matched to the first barrier layer and to a substrate of a III-V compound semiconductor material. The second cladding layer is lattice matched to the second barrier layer. The quantum well layer comprises a II-VI compound semiconductor material having the formula A.sub.x B.sub.(1-x) C wherein A and B are two different elements from Group II and C is at least one element from Group VI. When the second cladding layer has a p-type conductivity, a graded bandgap ohmic contact according to the present invention can be utilized. The graded bandgap contact can be a single continuously graded II-VI p-type region or a plurality of cells with each of the cells having first and second thin layers of first and second p-type II-VI semiconductor materials respectively. Another embodiment of the present invention discloses a monolithic multicolor light emitting element capable of emitting four colors and a method for fabricating same. The monolithic multicolor element includes four II-VI semiconductor light emitting devices formed on a single III-V substrate.

Abstract translation: 公开了包括设置在第一和第二阻挡层之间的阱层的至少一个II-VI量子阱区的II-VI族化合物半导体发光器件。 量子阱区夹在II-VI半导体材料的第一和第二覆层之间。 第一包层与第一阻挡层和III-V族化合物半导体材料的衬底形成并晶格匹配。 第二包层与第二阻挡层晶格匹配。 量子阱层包括具有式AxB（1-x）C的II-VI化合物半导体材料，其中A和B是来自组II的两个不同元素，C是来自第VI族的至少一种元素。 当第二包覆层具有p型导电性时，可以使用根据本发明的渐变带隙欧姆接触。 分级带隙接触可以是单个连续分级的II-VI p型区域或多个单元，其中每个单元分别具有第一和第二p型II-VI半导体材料的第一和第二薄层。 本发明的另一实施例公开了能够发射四种颜色的单片多色发光元件及其制造方法。 单片多色元件包括形成在单个III-V衬底上的四个II-VI半导体发光器件。

公开(公告)号：US09231519B2

公开(公告)日：2016-01-05

申请号：US13976942

申请日：2012-03-13

Applicant: Fangxing Wei ,  Yongping Fan

Inventor： Fangxing Wei ,  Yongping Fan

IPC: H03L1/00 ,  H03B5/04 ,  H03B5/12

CPC classification number: H03B5/04 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1265

Abstract: A temperature compensation apparatus may include a sense circuit configured to produce a sense voltage that is dependent on temperature and a temperature compensation circuit configured to receive the sense voltage and produce a temperature compensation control signal to control a compensation capacitor array of an oscillator. The temperature compensation circuit may be configured to calibrate the control signal to have a first value at a first temperature. The temperature compensation circuit may also be configured to calibrate a trimming level (e.g., slope) of the control signal.

Abstract translation: 温度补偿装置可以包括被配置为产生取决于温度的感测电压的感测电路和被配置为接收感测电压并产生温度补偿控制信号以控制振荡器的补偿电容器阵列的温度补偿电路。 温度补偿电路可以被配置为校准控制信号以具有处于第一温度的第一值。 温度补偿电路还可以被配置为校准控制信号的微调电平（例如，斜率）。

公开(公告)号：US20140266472A1

公开(公告)日：2014-09-18

申请号：US13837070

申请日：2013-03-15

Applicant: Jeffrey W. Waldrip ,  Yongping Fan ,  Jing Li

Inventor： Jeffrey W. Waldrip ,  Yongping Fan ,  Jing Li

IPC: H03L1/02

CPC classification number: H03L1/022 ,  H03B5/04 ,  H03B5/08 ,  H03L7/087 ,  H03L7/099 ,  H03L7/103 ,  H03L2207/06 ,  H04L7/033

Abstract: In some embodiments, provided are AFC circuits and methods for calibrating a second setting of an oscillator while a first setting is controlled by a temperature compensated control.

Abstract translation: 在一些实施例中，提供了AFC电路和用于校准振荡器的第二设置的方法，而第一设置由温度补偿控制来控制。

公开(公告)号：US20140218082A1

公开(公告)日：2014-08-07

申请号：US13997645

申请日：2011-12-30

Applicant: Yongping Fan

Inventor： Yongping Fan

IPC: H03L7/093

CPC classification number: H03L7/093 ,  H03H19/004 ,  H03L7/0893

Abstract: A loop filter is described. The loop filter has first and second inputs and an output. A loop filter capacitor is coupled to the loop filter output. Sample switches are coupled to the second loop filter input. A voltage divider is coupled to reset switches. Switched capacitors are coupled to sample switches, the reset switches, the loop filter capacitor, and the loop filter output.

Abstract translation: 描述环路滤波器。 环路滤波器具有第一和第二输入和输出。 环路滤波电容器耦合到环路滤波器输出。 采样开关耦合到第二环路滤波器输入。 分压器耦合到复位开关。 开关电容器耦合到采样开关，复位开关，环路滤波电容器和环路滤波器输出。

公开(公告)号：US07501869B2

公开(公告)日：2009-03-10

申请号：US11592594

申请日：2006-11-03

Applicant: Yongping Fan ,  Ian Young

Inventor： Yongping Fan ,  Ian Young

IPC: H03L7/06

CPC classification number: H03L7/0812 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/0891

Abstract: A clock receiver architecture for source synchronous digital data communication, the receiver including a forwarded clock amplifier to provide the received forwarded clock signal to a plurality of delay locked loops. Each delay locked loops provides to one or more phase interpolators a set of clock signals generated from the received forwarded clock, where the relative phases of the set of clock signals are uniformly spaced. Phase interpolators interpolate between two adjacent (with respect to phase) clock signals so as to provide a clock signal to sample received data at the center of the data eye. In some embodiments, an on-die voltage regulator provides a regulated supply voltage to the delay locked loops and phase interpolators. In some embodiments, pull-up currents and pull-down currents in the phase locked loops and phase interpolators are matched across process, supply voltage, and temperature variations so that the relative phases of the clock signals are insensitive across process, supply voltage, and temperature variations. Other embodiments are described and claimed.

Abstract translation: 一种用于源同步数字数据通信的时钟接收器架构，接收器包括转发的时钟放大器，以将接收到的转发时钟信号提供给多个延迟锁定环路。 每个延迟锁定环路向一个或多个相位内插器提供从接收的转发时钟生成的一组时钟信号，其中该组时钟信号的相对相位是均匀间隔的。 相位插值器在两个相邻（相对于相位）时钟信号之间插值，以便提供一个时钟信号来对数据眼睛中心的接收数据进行采样。 在一些实施例中，片上电压调节器向延迟锁定环路和相位内插器提供稳定的电源电压。 在一些实施例中，锁相环和相位内插器中的上拉电流和下拉电流在过程，电源电压和温度变化之间匹配，使得时钟信号的相对相位在过程，电源电压和 温度变化。 描述和要求保护其他实施例。

公开(公告)号：US20070216454A1

公开(公告)日：2007-09-20

申请号：US11374808

申请日：2006-03-14

Applicant: Yongping Fan ,  Ian Young

Inventor： Yongping Fan ,  Ian Young

IPC: H03L7/06

CPC classification number: H03L7/0812 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  H03L7/0891 ,  H03L7/10

Abstract: A fast lock mechanism for delay lock loops and phase lock loops. A first circuit is coupled to receive an input clock signal and to generate an output clock signal responsive to the input clock signal. The first circuit includes a charge pump and delay cells. The charge pump generates an operational bias voltage during operation of the first circuit to control a delay of the delay cells. A fast lock circuit is coupled to an output of the charge pump to precharge the output of the charge pump with a startup bias voltage prior to enabling the charge pump.

Abstract translation: 用于延迟锁定环和锁相环的快速锁定机制。 第一电路被耦合以接收输入时钟信号并响应于输入时钟信号产生输出时钟信号。 第一电路包括电荷泵和延迟单元。 电荷泵在第一电路的操作期间产生操作偏置电压以控制延迟单元的延迟。 快速锁定电路耦合到电荷泵的输出端，以在启用电荷泵之前以启动偏置电压对电荷泵的输出进行预充电。

公开(公告)号：US09379717B2

公开(公告)日：2016-06-28

申请号：US14129505

申请日：2013-11-08

Applicant: Gennady Goltman ,  Yongping Fan ,  Kuan-Yueh Shen

Inventor： Gennady Goltman ,  Yongping Fan ,  Kuan-Yueh Shen

IPC: H03L7/00 ,  H03L7/08 ,  H03L7/085 ,  H03L7/089

CPC classification number: H03L7/0802 ,  H03L7/085 ,  H03L7/089 ,  H03L7/0895 ,  H03L7/093

Abstract: Described is an apparatus to lower power of a charge pump. The apparatus comprises: a first delay unit to receive a reference clock, the first delay unit to provide a delayed reference clock to a first sequential unit; a second delay unit to receive a feedback clock, the second delay unit to provide a delayed feedback clock to a second sequential unit; a first logic unit to receive the reference and feedback clocks, the logic unit to perform a logical OR operation on the received reference and feedback clocks, and to generate a trigger signal for a third sequential unit; and a second logic unit to receive outputs of first and second sequential units, and to generate an output coupled to the third sequential unit.

Abstract translation: 描述了一种降低电荷泵功率的装置。 所述装置包括：第一延迟单元，用于接收参考时钟，所述第一延迟单元向第一顺序单元提供延迟的参考时钟; 第二延迟单元，用于接收反馈时钟，所述第二延迟单元向第二顺序单元提供延迟的反馈时钟; 用于接收参考和反馈时钟的第一逻辑单元，所述逻辑单元对所接收的参考和反馈时钟执行逻辑或运算，并且产生用于第三顺序单元的触发信号; 以及第二逻辑单元，用于接收第一和第二顺序单元的输出，并且产生耦合到第三顺序单元的输出。

公开(公告)号：US08274339B2

公开(公告)日：2012-09-25

申请号：US12770230

申请日：2010-04-29

Applicant: Yongping Fan ,  Jing Li ,  Ian A. Young

Inventor： Yongping Fan ,  Jing Li ,  Ian A. Young

IPC: H03L1/02 ,  H03L7/085

CPC classification number: H03L1/02 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1234 ,  H03B5/124 ,  H03B5/1265 ,  H03J2200/10 ,  H03L7/099 ,  H03L7/103 ,  H03L7/18

Abstract: A mixed signal circuit architecture is disclosed for automatic frequency control and digital temperature compensation in an LC-PLL system. Some embodiments allow for high-volume manufacturing of products such as microprocessors and chipsets, and other circuits that employ LC-PLL technology. In some embodiments, various capacitor loadings can be selected to compensate for variation associated with process, voltage, temperature, and reference frequency. In addition, a multi-leg capacitor bank can be selectively used to further compensate for temperature variation post-lock, in accordance with some embodiments. A programmable timer can be used in some embodiments to allow for loop settling prior to assessing parameters of interest.

Abstract translation: 公开了用于LC-PLL系统中的自动频率控制和数字温度补偿的混合信号电路架构。 一些实施例允许诸如微处理器和芯片组的产品的大量制造以及采用LC-PLL技术的其它电路。 在一些实施例中，可以选择各种电容器负载以补偿与过程，电压，温度和参考频率相关联的变化。 此外，根据一些实施例，可以选择性地使用多支脚电容器组来进一步补偿温度变化后锁定。 在一些实施例中可以使用可编程定时器，以便在评估感兴趣的参数之前允许循环结算。

公开(公告)号：US20080122507A1

公开(公告)日：2008-05-29

申请号：US11592594

申请日：2006-11-03

Applicant: Yongping Fan ,  Ian Young

Inventor： Yongping Fan ,  Ian Young

IPC: H03L7/06

CPC classification number: H03L7/0812 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/0891

Abstract: A clock receiver architecture for source synchronous digital data communication, the receiver including a forwarded clock amplifier to provide the received forwarded clock signal to a plurality of delay locked loops. Each delay locked loops provides to one or more phase interpolators a set of clock signals generated from the received forwarded clock, where the relative phases of the set of clock signals are uniformly spaced. Phase interpolators interpolate between two adjacent (with respect to phase) clock signals so as to provide a clock signal to sample received data at the center of the data eye. In some embodiments, an on-die voltage regulator provides a regulated supply voltage to the delay locked loops and phase interpolators. In some embodiments, pull-up currents and pull-down currents in the phase locked loops and phase interpolators are matched across process, supply voltage, and temperature variations so that the relative phases of the clock signals are insensitive across process, supply voltage, and temperature variations. Other embodiments are described and claimed.

Abstract translation: 一种用于源同步数字数据通信的时钟接收器架构，接收器包括转发的时钟放大器，以将接收到的转发时钟信号提供给多个延迟锁定环路。 每个延迟锁定环路向一个或多个相位内插器提供从接收的转发时钟生成的一组时钟信号，其中该组时钟信号的相对相位是均匀间隔的。 相位插值器在两个相邻（相对于相位）时钟信号之间插值，以便提供一个时钟信号来对数据眼睛中心的接收数据进行采样。 在一些实施例中，片上电压调节器向延迟锁定环路和相位内插器提供稳定的电源电压。 在一些实施例中，锁相环和相位内插器中的上拉电流和下拉电流在过程，电源电压和温度变化之间匹配，使得时钟信号的相对相位在过程，电源电压和 温度变化。 描述和要求保护其他实施例。