公开(公告)号：US07675777B2

公开(公告)日：2010-03-09

申请号：US11528924

申请日：2006-09-28

Applicant: You Sang Lee ,  Sang Won Hwang

Inventor： You Sang Lee ,  Sang Won Hwang

IPC: G11C16/04

CPC classification number: G11C16/10 ,  G11C16/26 ,  G11C2216/14

Abstract: A non-volatile semiconductor memory device, including a memory array having a plurality of first bit line groups and a plurality of second bit line groups that are alternately arranged to be adjacent each other, a plurality of data lines, a plurality of first page buffers, a plurality of second page buffers, and a plurality of switches. Each of the first page buffers is electrically connected to a corresponding one of the first bit line groups and arranged on a first side of the memory array. The first page buffers transmit data to the data lines. Each of the second page buffers is electrically connected to a corresponding one of the second bit line groups and arranged on a second side of the memory array. Each of the switches enables data transmission between a corresponding one of the first page buffers and a corresponding one of the second page buffers.

Abstract translation: 一种非易失性半导体存储器件，包括具有多个第一位线组的存储器阵列和交替布置为彼此相邻的多个第二位线组，多个数据线，多个第一页缓冲器 ，多个第二页缓冲器和多个开关。 第一页缓冲器中的每一个电连接到第一位线组中的对应的一个并且布置在存储器阵列的第一侧上。 第一页缓冲区将数据发送到数据线。 第二页缓冲器中的每一个电连接到相应的一个第二位线组并且布置在存储器阵列的第二侧上。 每个开关使得能够在第一页缓冲器中的相应一个和第二页缓冲器之间的对应的一个之间进行数据传输。

公开(公告)号：US07817471B2

公开(公告)日：2010-10-19

申请号：US12208574

申请日：2008-09-11

Applicant: You-Sang Lee ,  Yoon-Hee Choi

Inventor： You-Sang Lee ,  Yoon-Hee Choi

IPC: G11C16/04

CPC classification number: G11C16/10 ,  G11C5/145 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/12

Abstract: Provided are a flash memory device and method of controlling certain program operation voltages. The flash memory device includes a high voltage generation circuit providing a high voltage to a block selection circuit and a program voltage to a row decoder. The high voltage generation circuit includes a charge pump, a high voltage control circuit controlling the charge pump to provide the high voltage, and a program voltage control circuit providing the program voltage in relation to the high voltage, wherein the high voltage control circuit and the program voltage control circuit operate in response to the same control code.

Abstract translation: 提供了一种控制某些程序操作电压的闪存器件和方法。 闪速存储器件包括向块选择电路提供高电压的高电压产生电路和对行解码器的编程电压。 高电压产生电路包括电荷泵，控制电荷泵以提供高电压的高压控制电路以及提供与高电压相关的编程电压的编程电压控制电路，其中高电压控制电路和 程序电压控制电路响应于相同的控制代码而工作。

公开(公告)号：US20090080256A1

公开(公告)日：2009-03-26

申请号：US12208574

申请日：2008-09-11

Applicant: You-Sang LEE ,  Yoon-Hee CHOI

Inventor： You-Sang LEE ,  Yoon-Hee CHOI

IPC: G11C16/04 ,  G11C16/06 ,  G11C8/00 ,  G11C7/00

CPC classification number: G11C16/10 ,  G11C5/145 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/12

Abstract: Provided are a flash memory device and method of controlling certain program operation voltages. The flash memory device includes a high voltage generation circuit providing a high voltage to a block selection circuit and a program voltage to a row decoder. The high voltage generation circuit includes a charge pump, a high voltage control circuit controlling the charge pump to provide the high voltage, and a program voltage control circuit providing the program voltage in relation to the high voltage, wherein the high voltage control circuit and the program voltage control circuit operate in response to the same control code.

Abstract translation: 提供了一种控制某些程序操作电压的闪存器件和方法。 闪速存储器件包括向块选择电路提供高电压的高电压产生电路和对行解码器的编程电压。 高电压产生电路包括电荷泵，控制电荷泵以提供高电压的高压控制电路以及提供与高电压相关的编程电压的编程电压控制电路，其中高电压控制电路和 程序电压控制电路响应于相同的控制代码而工作。

公开(公告)号：US20080094071A1

公开(公告)日：2008-04-24

申请号：US11605224

申请日：2006-11-29

Applicant: You-sang Lee ,  Jin-Yub Lee

Inventor： You-sang Lee ,  Jin-Yub Lee

IPC: G01R31/02

CPC classification number: G01R31/318566

Abstract: A semiconductor device includes a plurality of fuses, and a plurality of latch circuits respectively electrically connected to the plurality of fuses. The plurality of latch circuits are configured to store respective fuse-cut information from the plurality of fuses, and to then sequentially transmit the fuse-cut information through the latch circuits to output sequential data indicative of a fuse-cut state of the plurality of fuses.

Abstract translation: 半导体器件包括多个保险丝，以及分别电连接到多个保险丝的多个锁存电路。 多个锁存电路被配置为存储来自多个保险丝的相应熔丝切断信息，然后通过锁存电路顺序地发送熔丝切断信息，以输出表示多个保险丝的熔丝切断状态的顺序数据 。

公开(公告)号：US07315480B2

公开(公告)日：2008-01-01

申请号：US11444353

申请日：2006-06-01

Applicant: You-Sang Lee ,  Sang-Won Hwang

Inventor： You-Sang Lee ,  Sang-Won Hwang

IPC: G11C7/00 ,  G11C8/00

CPC classification number: G11C29/846

Abstract: A redundancy selector circuit for use in a non-volatile memory device include a ROM cell array, in which defective addresses are stored, including a plurality of ROM cells arranged in a matrix of rows and columns; a ROM controller for sequentially selecting rows of the ROM cell array at power-up; a sense amplifier block for sensing and amplifying data bits from ROM cells of the respective rows selected sequentially according to the control of the ROM controller; a latch block for receiving data bits sensed by the sense amplifier block through a switch circuit and latching the input data bits as a defective address; and a comparator block for detecting whether an address input in a normal operation matches one of the defective addresses stored in the latch block. As the rows are sequentially selected, the defective addresses of the ROM cell array are transferred to the latch block through the sense amplifier block by means of serial transfer.

Abstract translation: 在非易失性存储装置中使用的冗余选择器电路包括ROM阵列，其中存储有不良地址的ROM单元阵列，包括以行和列为矩阵排列的多个ROM单元; ROM控制器，用于在加电时依次选择ROM单元阵列的行; 读出放大器模块，用于根据ROM控制器的控制来依次选择依次选择的各个ROM单元的数据位; 锁存块，用于通过开关电路接收由读出放大器块检测的数据位，并将输入数据位锁存为缺陷地址; 以及用于检测在正常操作中输入的地址是否匹配存储在锁存块中的缺陷地址中的一个的比较器块。 当依次选择行时，ROM单元阵列的缺陷地址通过串行传输通过读出放大器块传送到锁存块。

公开(公告)号：US07990129B2

公开(公告)日：2011-08-02

申请号：US12476565

申请日：2009-06-02

Applicant: Joon Young Kwak ,  Yoon-Hee Choi ,  Jin-Yub Lee ,  You-Sang Lee ,  Bo-Geun Kim

Inventor： Joon Young Kwak ,  Yoon-Hee Choi ,  Jin-Yub Lee ,  You-Sang Lee ,  Bo-Geun Kim

IPC: G05F3/16

CPC classification number: G05F3/08

Abstract: A reference voltage generating circuit provides a stabilized reference voltage and includes; a clock generator providing a clock signal, a high voltage generator providing a pumping voltage in response to the clock signal, a ripple eradicator providing a static voltage by removing voltage ripple from the pumping voltage, and a reference voltage generator providing the reference voltage.

Abstract translation: 参考电压产生电路提供稳定的参考电压并且包括： 提供时钟信号的时钟发生器，响应于时钟信号提供泵浦电压的高电压发生器，通过从所述泵浦电压去除电压纹波提供静态电压的纹波消除器以及提供参考电压的参考电压发生器。

公开(公告)号：US20070019483A1

公开(公告)日：2007-01-25

申请号：US11444353

申请日：2006-06-01

Applicant: You-Sang Lee ,  Sang-Won Hwang

Inventor： You-Sang Lee ,  Sang-Won Hwang

IPC: G11C7/00 ,  G11C7/10

CPC classification number: G11C29/846

Abstract: A redundancy selector circuit for use in a non-volatile memory device include a ROM cell array, in which defective addresses are stored, including a plurality of ROM cells arranged in a matrix of rows and columns; a ROM controller for sequentially selecting rows of the ROM cell array at power-up; a sense amplifier block for sensing and amplifying data bits from ROM cells of the respective rows selected sequentially according to the control of the ROM controller; a latch block for receiving data bits sensed by the sense amplifier block through a switch circuit and latching the input data bits as a defective address; and a comparator block for detecting whether an address input in a normal operation matches one of the defective addresses stored in the latch block. As the rows are sequentially selected, the defective addresses of the ROM cell array are transferred to the latch block through the sense amplifier block by means of serial transfer.

Abstract translation: 在非易失性存储装置中使用的冗余选择器电路包括ROM阵列，其中存储有不良地址的ROM单元阵列，包括以行和列为矩阵排列的多个ROM单元; ROM控制器，用于在加电时依次选择ROM单元阵列的行; 读出放大器模块，用于根据ROM控制器的控制来依次选择依次选择的各个ROM单元的数据位; 锁存块，用于通过开关电路接收由读出放大器块检测的数据位，并将输入数据位锁存为缺陷地址; 以及用于检测在正常操作中输入的地址是否匹配存储在锁存块中的缺陷地址中的一个的比较器块。 当依次选择行时，ROM单元阵列的缺陷地址通过串行传输通过读出放大器块传送到锁存块。

公开(公告)号：US07511509B2

公开(公告)日：2009-03-31

申请号：US11605224

申请日：2006-11-29

Applicant: You-sang Lee ,  Jin-yub Lee

Inventor： You-sang Lee ,  Jin-yub Lee

IPC: G01R31/02

CPC classification number: G01R31/318566

Abstract: A semiconductor device includes a plurality of fuses, and a plurality of latch circuits respectively electrically connected to the plurality of fuses. The plurality of latch circuits are configured to store respective fuse-cut information from the plurality of fuses, and to then sequentially transmit the fuse-cut information through the latch circuits to output sequential data indicative of a fuse-cut state of the plurality of fuses.

Abstract translation: 半导体器件包括多个保险丝，以及分别电连接到多个保险丝的多个锁存电路。 多个锁存电路被配置为存储来自多个保险丝的相应熔丝切断信息，然后通过锁存电路顺序地发送熔丝切断信息，以输出表示多个保险丝的熔丝切断状态的顺序数据 。

公开(公告)号：US20100001710A1

公开(公告)日：2010-01-07

申请号：US12476565

申请日：2009-06-02

Applicant: Joon Young KWAK ,  Yoon-Hee CHOI ,  Jin-Yub LEE ,  You-Sang LEE ,  Bo-Geun KIM

Inventor： Joon Young KWAK ,  Yoon-Hee CHOI ,  Jin-Yub LEE ,  You-Sang LEE ,  Bo-Geun KIM

IPC: G05F3/16

CPC classification number: G05F3/08

Abstract: A reference voltage generating circuit provides a stabilized reference voltage and includes; a clock generator providing a clock signal, a high voltage generator providing a pumping voltage in response to the clock signal, a ripple eradicator providing a static voltage by removing voltage ripple from the pumping voltage, and a reference voltage generator providing the reference voltage.

Abstract translation: 参考电压产生电路提供稳定的参考电压并且包括： 提供时钟信号的时钟发生器，响应于时钟信号提供泵浦电压的高电压发生器，通过从所述泵浦电压去除电压纹波提供静态电压的纹波消除器以及提供参考电压的参考电压发生器。

公开(公告)号：US20050135145A1

公开(公告)日：2005-06-23

申请号：US10957382

申请日：2004-09-30

Applicant: You-Sang Lee ,  Jin-Yub Lee

Inventor： You-Sang Lee ,  Jin-Yub Lee

IPC: G11C16/02 ,  G11C8/18 ,  G11C11/00 ,  G11C16/32

CPC classification number: G11C16/32 ,  G11C8/18

Abstract: A flash memory device includes a flash memory cell array, and an interface circuit, which receives a command and addresses sequentially in synchronization to an external system clock after a predetermined first latency is elapsed from when a chip enable signal is activated, in a read operation, in a program operation, and in an erase operation. The interface circuit receives the command in response to activation of an invoke signal. Therefore, since the flash memory device does not require CLE (Command Latch Enable) signals, ALE (Address Latch Enable) signals, RE (Read Enable) signals and WE (Write Enable) signals, internal circuits of the flash memory device can be simply controlled, thereby reducing a probability of skew generation in chips, improving performance, and decreasing the number of required pins.

Abstract translation: 闪速存储器件包括闪速存储单元阵列和接口电路，该接口电路在读取操作中从启动芯片使能信号起经过预定​​的第一等待时间之后，以与外部系统时钟同步的顺序接收命令和寻址 ，在编程操作中，以及擦除操作。 接口电路响应于调用信号的激活而接收命令。 因此，由于闪存器件不需要CLE（命令锁存使能）信号，ALE（地址锁存使能）信号，RE（读使能）信号和WE（写使能）信号，闪存器件的内部电路可以简单 从而降低了芯片中产生偏斜的可能性，提高了性能，并减少了所需引脚的数量。