公开(公告)号：US20120329261A1

公开(公告)日：2012-12-27

申请号：US13164781

申请日：2011-06-21

申请人： Shao-Wei Wang ,  Yu-Ren Wang ,  Chien-Liang Lin ,  Wen-Yi Teng ,  Tsuo-Wen Lu ,  Chih-Chung Chen ,  Ying-Wei Yen ,  Yu-Min Lin ,  Chin-Cheng Chien ,  Jei-Ming Chen ,  Chun-Wei Hsu ,  Chia-Lung Chang ,  Yi-Ching Wu ,  Shu-Yen Chan

发明人： Shao-Wei Wang ,  Yu-Ren Wang ,  Chien-Liang Lin ,  Wen-Yi Teng ,  Tsuo-Wen Lu ,  Chih-Chung Chen ,  Ying-Wei Yen ,  Yu-Min Lin ,  Chin-Cheng Chien ,  Jei-Ming Chen ,  Chun-Wei Hsu ,  Chia-Lung Chang ,  Yi-Ching Wu ,  Shu-Yen Chan

IPC分类号： H01L21/782 ,  H01L21/28

CPC分类号： H01L29/7833 ,  H01L21/265 ,  H01L21/3215 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659

摘要： A manufacturing method for a metal gate includes providing a substrate having at least a semiconductor device with a conductivity type formed thereon, forming a gate trench in the semiconductor device, forming a work function metal layer having the conductivity type and an intrinsic work function corresponding to the conductivity type in the gate trench, and performing an ion implantation to adjust the intrinsic work function of the work function metal layer to a target work function.

摘要翻译： 一种金属栅极的制造方法，包括提供具有至少形成有导电类型的半导体器件的衬底，在该半导体器件中形成栅极沟槽，形成具有导电类型的功函数金属层和对应于 栅极沟槽中的导电类型，并且执行离子注入以将功函数金属层的固有功函数调整到目标功函数。

公开(公告)号：US07848146B2

公开(公告)日：2010-12-07

申请号：US12407228

申请日：2009-03-19

申请人： Youseok Suh ,  Ya-Fen Lin ,  Coling Stewart Bill ,  Takao Akaogi ,  Yi-Ching Wu

发明人： Youseok Suh ,  Ya-Fen Lin ,  Coling Stewart Bill ,  Takao Akaogi ,  Yi-Ching Wu

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C16/0483

摘要： A method for partial local self-boosting of a memory cell channel is disclosed. As a part of memory cell channel partial local self-boosting, an isolating memory cell located on a source side of a program inhibited memory cell is turned off and a gating memory cell located on a drain side of the program inhibited memory cell is used to pass a pre-charge voltage to the program inhibited memory cell to provide a pre-charge voltage to a channel of the program inhibited memory cell. Moreover, a pre-charge voltage is passed to a buffering memory cell located on the source side of the program inhibited memory cell to provide a pre-charge voltage to a channel of the buffering memory cell and the gating memory cell that is located on the drain side of the program inhibited memory cell is turned off. During programming, a program voltage is applied to the gate of the program inhibited memory cell where a channel voltage of the program inhibited memory cell is raised above a level raised by the pre-charge voltage.

摘要翻译： 公开了一种用于存储器单元通道的局部局部自升压的方法。 作为存储单元通道部分局部自升压的一部分，位于程序禁止存储单元的源极侧的隔离存储单元被截止，并且位于程序禁止存储单元的漏极侧的门控存储单元被用于 将预充电电压传递到程序禁止的存储单元，以向编程禁止的存储单元的通道提供预充电电压。 此外，预充电电压被传递到位于程序禁止的存储单元的源极侧的缓冲存储单元，以向缓冲存储单元的通道和位于该存储单元上的选通存储单元提供预充电电压 程序的漏极侧禁止存储单元关闭。 在编程期间，将程序禁止存储单元的通道电压升高到由预充电电压升高的电平以上的程序禁止存储单元的栅极上施加编程电压。

公开(公告)号：US07468326B2

公开(公告)日：2008-12-23

申请号：US11161961

申请日：2005-08-24

申请人： Ming-Te Chen ,  Yi-Ching Wu ,  Chien-Tung Huang

发明人： Ming-Te Chen ,  Yi-Ching Wu ,  Chien-Tung Huang

IPC分类号： H01L21/30

CPC分类号： H01L21/02057 ,  C23C16/0227 ,  H01L21/0206 ,  H01L21/02087 ,  H01L21/0209 ,  H01L21/31612 ,  H01L21/76224 ,  H01L27/11521

摘要： A wafer is provided and loaded in a reaction chamber. Subsequently, the wafer is lifted up, and a dry clean process is performed on the wafer to clean the front side, the back side, and the bevel of the wafer. Following that, a deposition process is performed on the wafer. The dry clean process and the deposition process are carried out in an in-situ manner.

摘要翻译： 提供晶片并将其装载在反应室中。 随后，将晶片提起，并对晶片进行干洗处理以清洁晶片的正面，背面和斜面。 之后，在晶片上进行沉积工艺。 干洗过程和沉积过程以原位方式进行。

公开(公告)号：US07259097B2

公开(公告)日：2007-08-21

申请号：US11233625

申请日：2005-09-22

申请人： Ming-Hsin Yeh ,  Cheng-Chuan Lee ,  Yi-Ching Wu ,  Chih-Hsiang Hsiao

发明人： Ming-Hsin Yeh ,  Cheng-Chuan Lee ,  Yi-Ching Wu ,  Chih-Hsiang Hsiao

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： B23H5/08 ,  H01L21/76819 ,  H01L21/7684 ,  Y10S438/959

摘要： A method for controlling an apparatus to perform a multi-layer chemical mechanical polishing (CMP) process with a polishing rate for a plurality of process runs. For each process run, a multilayered structure with a first thickness formed on a wafer is polished and a second thickness of the multilayered structure is predetermined to be polished away. The method comprises steps of receiving a post-CMP thickness information of the multilayered structure of a first process run, wherein for the first process run, the CMP process is performed for a first CMP process time. Then, a second CMP process time is determined according to the first CMP process time, the first thickness and the post-CMP thickness. Further, the second CMP process time is provided to the apparatus for processing a second process run posterior to the first process run.

公开(公告)号：US20070166998A1

公开(公告)日：2007-07-19

申请号：US11695509

申请日：2007-04-02

申请人： YI-CHING WU ,  CHRIS CHEN ,  CHIH-HSIANG SHIAU ,  NUNO CHEN ,  LEONARD CHEN

发明人： YI-CHING WU ,  CHRIS CHEN ,  CHIH-HSIANG SHIAU ,  NUNO CHEN ,  LEONARD CHEN

IPC分类号： H01L21/469

CPC分类号： H01L21/76832 ,  H01L21/76834 ,  H01L21/76883 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnecting process is described. First, a dielectric layer with a plurality of openings is provided. Then, a metallic layer is formed to fill up the openings. A first dielectric barrier layer is formed to cover the dielectric layer and the metallic layer. Thereafter, a second dielectric barrier layer is formed over the first dielectric barrier layer. The second dielectric barrier layer is used to repair the first dielectric barrier layer and improve the reliability and yield of the process.

摘要翻译： 描述了互连过程。 首先，提供具有多个开口的电介质层。 然后，形成金属层以填充开口。 形成第一电介质阻挡层以覆盖电介质层和金属层。 此后，在第一电介质阻挡层上形成第二电介质阻挡层。 第二电介质阻挡层用于修复第一介电阻挡层并提高工艺的可靠性和产率。

公开(公告)号：US20060194427A1

公开(公告)日：2006-08-31

申请号：US11066995

申请日：2005-02-25

申请人： Yi-Ching Wu ,  Chris Chen ,  Chih-Hsiang Shiau ,  Nuno Chen ,  Leonard Chen

发明人： Yi-Ching Wu ,  Chris Chen ,  Chih-Hsiang Shiau ,  Nuno Chen ,  Leonard Chen

IPC分类号： H01L21/4763

CPC分类号： H01L21/76832 ,  H01L21/76834 ,  H01L21/76883 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnecting process is described. First, a dielectric layer with a plurality of openings is provided. Then, a metallic layer is formed to fill up the openings. A first dielectric barrier layer is formed to cover the dielectric layer and the metallic layer. Thereafter, a second dielectric barrier layer is formed over the first dielectric barrier layer. The second dielectric barrier layer is used to repair the first dielectric barrier layer and improve the reliability and yield of the process.

摘要翻译： 描述了互连过程。 首先，提供具有多个开口的电介质层。 然后，形成金属层以填充开口。 形成第一电介质阻挡层以覆盖电介质层和金属层。 此后，在第一电介质阻挡层上形成第二电介质阻挡层。 第二电介质阻挡层用于修复第一介电阻挡层并提高工艺的可靠性和产率。

公开(公告)号：US08076213B2

公开(公告)日：2011-12-13

申请号：US12554968

申请日：2009-09-07

申请人： Lian-Hua Shih ,  Yi-Ching Wu ,  Jiann-Fu Chen ,  Ming-Te Chen ,  Chin-Jen Cheng

发明人： Lian-Hua Shih ,  Yi-Ching Wu ,  Jiann-Fu Chen ,  Ming-Te Chen ,  Chin-Jen Cheng

IPC分类号： H01L21/8242

CPC分类号： H01L28/40 ,  Y10S438/957

摘要： A method for fabricating a metal-insulator-metal (MIM) capacitor includes providing a substrate comprising a bottom electrode, forming a dielectric layer positioned on the bottom electrode, and forming a top electrode positioned on the dielectric layer. The dielectric layer includes a silicon nitride film, the silicon nitride film has a plurality of Si—H bonds and a plurality of N—H bonds, and a ratio of Si—H bonds to N—H bonds being equal to or smaller than 0.5.

摘要翻译： 一种用于制造金属 - 绝缘体 - 金属（MIM）电容器的方法，包括提供包括底部电极的基板，形成位于所述底部电极上的电介质层，以及形成位于所述电介质层上的顶部电极。 介电层包括氮化硅膜，氮化硅膜具有多个Si-H键和多个N-H键，Si-H键与N-H键的比例等于或小于0.5 。

公开(公告)号：US20100238731A1

公开(公告)日：2010-09-23

申请号：US12407228

申请日：2009-03-19

申请人： Youseok Suh ,  Ya-Fen Lin ,  Colin Stewart Bill ,  Takao Akaogi ,  Yi-Ching Wu

发明人： Youseok Suh ,  Ya-Fen Lin ,  Colin Stewart Bill ,  Takao Akaogi ,  Yi-Ching Wu

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C16/0483

摘要： A method for partial local self-boosting of a memory cell channel is disclosed. As a part of memory cell channel partial local self-boosting, an isolating memory cell located on a source side of a program inhibited memory cell is turned off and a gating memory cell located on a drain side of the program inhibited memory cell is used to pass a pre-charge voltage to the program inhibited memory cell to provide a pre-charge voltage to a channel of the program inhibited memory cell. Moreover, a pre-charge voltage is passed to a buffering memory cell located on the source side of the program inhibited memory cell to provide a pre-charge voltage to a channel of the buffering memory cell and the gating memory cell that is located on the drain side of the program inhibited memory cell is turned off. During programming, a program voltage is applied to the gate of the program inhibited memory cell where a channel voltage of the program inhibited memory cell is raised above a level raised by the pre-charge voltage.

摘要翻译： 公开了一种用于存储器单元通道的局部局部自升压的方法。 作为存储单元通道部分局部自升压的一部分，位于程序禁止存储单元的源极侧的隔离存储单元被截止，并且位于程序禁止存储单元的漏极侧的门控存储单元被用于 将预充电电压传递到程序禁止的存储单元，以向编程禁止的存储单元的通道提供预充电电压。 此外，预充电电压被传递到位于程序禁止的存储单元的源极侧的缓冲存储单元，以向缓冲存储单元的通道和位于该存储单元上的选通存储单元提供预充电电压 程序的漏极侧禁止存储单元关闭。 在编程期间，将程序禁止存储单元的通道电压升高到由预充电电压升高的电平以上的程序禁止存储单元的栅极上施加编程电压。

公开(公告)号：US07273824B2

公开(公告)日：2007-09-25

申请号：US10710405

申请日：2004-07-08

申请人： Yi-Ching Wu ,  Jiann-Fu Chen ,  Chih-Hsiang Shiau

发明人： Yi-Ching Wu ,  Jiann-Fu Chen ,  Chih-Hsiang Shiau

IPC分类号： H01L21/304

CPC分类号： H01L21/76832 ,  B24B9/065 ,  H01L21/02087 ,  H01L21/02126 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/31144 ,  H01L21/3122 ,  H01L21/31633 ,  H01L21/3185 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76807 ,  Y10S438/928 ,  Y10S438/963 ,  Y10S438/978

摘要： A semiconductor structure and a method of fabrication there-for are provided. The semiconductor structure comprises a substrate, a dielectric layer disposed over the substrate, a hydrophilic material layer disposed over the dielectric layer, and a hardmask layer disposed over the hydrophilic material layer. It is noted that, the edge of the semiconductor structure may be polished after the hydrophilic material layer is formed over the dielectric layer and before the hardmask layer is formed over the hydrophilic material layer.

摘要翻译： 提供半导体结构及其制造方法。 半导体结构包括衬底，设置在衬底上的电介质层，设置在电介质层上的亲水材料层，以及设置在亲水材料层上的硬掩模层。 应注意，在亲水性材料层形成在电介质层之上之后并且硬掩模层形成在亲水材料层之上之后，可以抛光半导体结构的边缘。

公开(公告)号：US20070049042A1

公开(公告)日：2007-03-01

申请号：US11161961

申请日：2005-08-24

申请人： Ming-Te Chen ,  Yi-Ching Wu ,  Chien-Tung Huang

发明人： Ming-Te Chen ,  Yi-Ching Wu ,  Chien-Tung Huang

IPC分类号： H01L21/31

CPC分类号： H01L21/02057 ,  C23C16/0227 ,  H01L21/0206 ,  H01L21/02087 ,  H01L21/0209 ,  H01L21/31612 ,  H01L21/76224 ,  H01L27/11521

摘要： A wafer is provided and loaded in a reaction chamber. Subsequently, the wafer is lifted up, and a dry clean process is performed on the wafer to clean the front side, the back side, and the bevel of the wafer. Following that, a deposition process is performed on the wafer. The dry clean process and the deposition process are carried out in an in-situ manner.

摘要翻译： 提供晶片并将其装载在反应室中。 随后，将晶片提起，并对晶片进行干洗处理以清洁晶片的正面，背面和斜面。 之后，在晶片上进行沉积工艺。 干洗过程和沉积过程以原位方式进行。