公开(公告)号：US5256895A

公开(公告)日：1993-10-26

申请号：US863519

申请日：1992-03-31

申请人： Frank R. Bryant ,  Yu-Pin Han ,  Fu-Tai Liou

发明人： Frank R. Bryant ,  Yu-Pin Han ,  Fu-Tai Liou

IPC分类号： H01L21/32 ,  H01L21/762 ,  H01L27/12 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L21/32 ,  H01L21/76205

摘要： Field oxide regions are formed between drive regions of a silicon substrate by forming over the substrate a sandwich of silicon dioxide, silicon nitride and silicon dioxide layers, opening the layers to expose a portion of the silicon substrate, removing a layer of the exposed substrate, forming side wall spacers on the edges of the opening, removing a layer of the silicon substrate exposed between the side wall spacers, and then reaching the exposed substrate for the thermal oxidation of the exposed substrate for forming the field oxide region. In those structures in which the field oxide is buried in the substrate as shown in FIG. 12, it may be feasible to use thicker field oxide regions and thereby to reduce the need for the heavily doped surface layer under the field oxide.

摘要翻译： 通过在衬底上形成二氧化硅，氮化硅和二氧化硅层的夹层来形成在硅衬底的驱动区之间的场氧化物区域，打开这些层以暴露硅衬底的一部分，去除暴露的衬底的一层， 在开口的边缘上形成侧壁间隔物，去除暴露在侧壁间隔物之间​​的硅衬底层，然后到达暴露的衬底，用于暴露衬底的热氧化以形成场氧化物区域。 在如图1所示的那些场地氧化物埋在衬底中的那些结构中。 如图12所示，可以使用较厚的场氧化物区域，从而减少对场氧化物下的重掺杂表面层的需要。

公开(公告)号：US4771014A

公开(公告)日：1988-09-13

申请号：US99144

申请日：1987-09-18

申请人： Fu-Tai Liou ,  Yu-Pin Han ,  Frank R. Bryant

发明人： Fu-Tai Liou ,  Yu-Pin Han ,  Frank R. Bryant

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L21/265 ,  H01L27/00

CPC分类号： H01L21/823878 ,  H01L27/0928

摘要： A method for making a CMOS integrated circuit device saves on masking steps by using unmasked blanket implantations at various steps of the process, such as setting the threshold voltages of the transistors, forming a lightly doped drain for the N-channel transistor, and for forming the source/drain regions of the N-type transistor.

公开(公告)号：US4981813A

公开(公告)日：1991-01-01

申请号：US279343

申请日：1988-12-02

申请人： Frank R. Bryant ,  Yu-Pin Han ,  Fu-Tai Liou ,  Tsiu C. Chan

发明人： Frank R. Bryant ,  Yu-Pin Han ,  Fu-Tai Liou ,  Tsiu C. Chan

IPC分类号： H01L21/32 ,  H01L21/762

CPC分类号： H01L21/76205 ,  H01L21/32

摘要： Field oxide regions are formed between active regions of a silicon substrate by forming over the substrate a sandwich of silicon dioxide, silicon nitride and silicon dioxide layers, opening the layers to expose a portion of the silicon substrate, removing a layer of the exposed substrate, forming side wall spacers on the edges of the opening, removing a layer of the silicon substrate exposed between the side wall spacers, and then reaching the exposed substrate for the thermal oxidation of the exposed substrate for forming the field oxide region. In those structures in which the field oxide is buried in the substrate as shown in FIG. 12, it may be feasible to use thicker field oxide regions and thereby to reduce the need for the heavily doped surface layer under the field oxide.

摘要翻译： 通过在衬底上形成二氧化硅，氮化硅和二氧化硅层的夹层来形成在硅衬底的有源区之间的场氧化物区域，打开这些层以露出硅衬底的一部分，去除暴露的衬底的一层， 在开口的边缘上形成侧壁间隔物，去除暴露在侧壁间隔物之间​​的硅衬底层，然后到达暴露的衬底，用于暴露衬底的热氧化以形成场氧化物区域。 在如图1所示的那些场地氧化物埋在衬底中的那些结构中。 如图12所示，可以使用较厚的场氧化物区域，从而减少对场氧化物下的重掺杂表面层的需要。

公开(公告)号：US5847465A

公开(公告)日：1998-12-08

申请号：US436165

申请日：1995-05-08

申请人： Fu-Tai Liou ,  Yu-Pin Han

发明人： Fu-Tai Liou ,  Yu-Pin Han

IPC分类号： H01L21/302 ,  H01L21/033 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/336 ,  H01L21/768 ,  H01L23/522 ,  H01L29/417 ,  H01L29/78 ,  H01L23/48 ,  H01L23/52 ,  H01L27/088 ,  H01L29/40

CPC分类号： H01L29/6659 ,  H01L21/033 ,  H01L21/3105 ,  H01L21/76804 ,  H01L29/41775 ,  H01L29/78 ,  H01L2924/0002 ,  Y10S257/90

摘要： A method for fabrication of metal to semiconductor contacts results in sloped sidewalls in contact regions. An oxide layer is deposited and etched back to form sidewall spacers. A glass layer is then deposited and heated to reflow. After reflow, an etch back of the glass layer results is sloped sidewalls at contact openings and over steps.

摘要翻译： 金属对半导体接触的制造方法导致接触区域的倾斜侧壁。 沉积氧化物层并回蚀刻以形成侧壁间隔物。 然后沉积玻璃层并加热回流。 在回流之后，玻璃层的回蚀是在接触开口和过度台阶上的倾斜侧壁。

公开(公告)号：US5371041A

公开(公告)日：1994-12-06

申请号：US831089

申请日：1992-02-07

申请人： Fu-Tai Liou ,  Robert O. Miller ,  Mohammed M. Farohani ,  Yu-Pin Han

发明人： Fu-Tai Liou ,  Robert O. Miller ,  Mohammed M. Farohani ,  Yu-Pin Han

IPC分类号： H01L21/768 ,  H01L23/485 ,  H01L23/532 ,  H01L21/44

CPC分类号： H01L21/76856 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/485 ,  H01L23/53223 ,  H01L2924/0002 ,  Y10S148/147 ,  Y10S257/915

摘要： A method for forming a connection between two levels in a semiconductor structure includes first forming a VIA (14) through an insulating layer (12) to an underlying structure (10). Sidewall spacers (22) and (24) are formed on the vertical walls of the VIA (14). The spacers (22) and (24) have tapered surfaces. A barrier layer (30) is then formed over the bottom surface of the VIA followed by CVD deposition of a conductive layer (32) of WSi.sub.2 to provide a conformal conductive layer. An aluminum layer (38) is then deposited by physical vapor deposition techniques with the descending portions of layer (32) providing a conductive connection between the aluminum layer (38) and the lower structure (10) in the VIA (14).

摘要翻译： 用于在半导体结构中形成两层之间的连接的方法包括首先通过绝缘层（12）形成VIA（14）到下面的结构（10）。 侧壁间隔件（22）和（24）形成在VIA（14）的垂直壁上。 间隔件（22）和（24）具有锥形表面。 然后在VIA的底表面上形成阻挡层（30），随后CVD沉积WSi2的导电层（32）以提供保形导电层。 然后通过物理气相沉积技术沉积铝层（38），层（32）的下降部分在VIA（14）中的铝层（38）和下结构（10）之间提供导电连接。

公开(公告)号：US4962414A

公开(公告)日：1990-10-09

申请号：US366194

申请日：1989-06-08

申请人： Fu-Tai Liou ,  Robert O. Miller ,  Mohammed M. Farohani ,  Yu-Pin Han

发明人： Fu-Tai Liou ,  Robert O. Miller ,  Mohammed M. Farohani ,  Yu-Pin Han

IPC分类号： H01L21/768 ,  H01L23/485 ,  H01L23/532

CPC分类号： H01L21/76856 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/485 ,  H01L23/53223 ,  H01L2924/0002 ,  Y10S148/147 ,  Y10S257/915

摘要： A method for forming a connection between two levels in a semiconductor structure includes first forming a VIA (14) through an insulating layer (12) to an underlying structure (10). Sidewall spacers (22) and (24) are formed on the vertical walls of the VIA (14). The spacers (22) and (24) have tapered surfaces. A barrier layer (30) is then formed over the bottom surface of the VIA followed by CVD deposition of a conductive layer (32) of WSi.sub.2 to provide a conformal conductive layer. An aluminum layer (38) is then deposited by physical vapor deposition techniques with the descending portions of layer (32) providing a conductive connection between the aluminum layer (38) and the lower structure (10) in the VIA (14).

摘要翻译： 用于在半导体结构中形成两层之间的连接的方法包括首先通过绝缘层（12）形成VIA（14）到下面的结构（10）。 侧壁间隔件（22）和（24）形成在VIA（14）的垂直壁上。 间隔件（22）和（24）具有锥形表面。 然后在VIA的底表面上形成阻挡层（30），随后CVD沉积WSi2的导电层（32）以提供保形导电层。 然后通过物理气相沉积技术沉积铝层（38），层（32）的下降部分在VIA（14）中的铝层（38）和下结构（10）之间提供导电连接。

公开(公告)号：US6007641A

公开(公告)日：1999-12-28

申请号：US818228

申请日：1997-03-14

申请人： Landon B. Vines ,  Felix H. Fujishiro ,  Yu-Pin Han

发明人： Landon B. Vines ,  Felix H. Fujishiro ,  Yu-Pin Han

IPC分类号： H01L21/28 ,  H01L21/306 ,  H01L21/316 ,  H01L29/51 ,  B08B3/00

CPC分类号： H01L21/28202 ,  H01L21/02063 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/02307 ,  H01L21/31612 ,  H01L21/31662 ,  H01L29/518

摘要： In the manufacture of an integrated circuit, contaminated oxide is replaced by relatively pure oxide using the following steps. First, a partially manufactured integrated circuit is bathed in an aqueous solution of hydrogen peroxide and ammonium hydroxide to oxidize organic materials and weaken bonds of metal contaminants to the integrated circuit substrate. Second, an aqueous rinse removes the oxidized organic materials and metal contaminants. Third, the integrated circuit is bathed in an aqueous solution of hydrogen fluoride and nitric acid. The hydrogen fluroide etches the contaminated oxide; the nitric acid combines with calcium and metal contaminants freed as the oxide is etched. The resulting nitride byproducts are highly soluble and easily removed in the following aqueous rinse. A drying step removes rinse water from the integrated circuit. Finally, an oxide formation step provides a relatively pure oxide layer. In the case of a gate oxide, the method removes a sacrificial oxide in preparation for gate oxide growth. In the case of formation of the submetal dielectric, oxide formation involves an TEOS oxide deposition. A key advantage of the invention is the improved calcium removal due to the nitric acid.

摘要翻译： 在集成电路的制造中，使用以下步骤用相对纯的氧化物代替污染的氧化物。 首先，将部分制造的集成电路沐浴在过氧化氢和氢氧化铵的水溶液中以氧化有机材料并减弱金属污染物与集成电路基板的接合。 第二，水性漂洗去除氧化的有机物质和金属污染物。 第三，将集成电路浸在氟化氢和硝酸的水溶液中。 氢氟酸蚀刻污染的氧化物; 硝酸与钙和金属污染物结合，氧化物被蚀刻掉。 所得的氮化物副产物是高度可溶的并且容易地在下列水性漂洗液中除去。 干燥步骤从集成电路中去除冲洗水。 最后，氧化物形成步骤提供相对纯的氧化物层。 在栅极氧化物的情况下，该方法除去用于栅极氧化物生长的牺牲氧化物。 在形成亚金属电介质的情况下，氧化物形成涉及TEOS氧化物沉积。 本发明的主要优点是由于硝酸而改善的钙去除。

公开(公告)号：US4868138A

公开(公告)日：1989-09-19

申请号：US172299

申请日：1988-03-23

申请人： Tsiu C. Chan ,  Yu-Pin Han

发明人： Tsiu C. Chan ,  Yu-Pin Han

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/8244 ,  H01L27/092 ,  H01L27/11

CPC分类号： H01L21/76897 ,  H01L21/28518 ,  H01L21/76802 ,  H01L29/6659

摘要： A process for forming electrical interconnect on MOS semiconductor integrated circuits includes the formation of a capping layer of oxide over the first level poly layer prior to patterning. The capping layer is then removed over selected regions. The conductive layer and capping oxide layer are then patterned to form transistor gates and interconnect. Source/drain regions are formed in active areas of the integrated circuit, and sidewall oxide is formed next to the patterned gate regions. When a second layer of interconnect is formed and patterned over the integrated circuit, contact between the first and second interconnect layers is made in the previously defined selected regions.

公开(公告)号：US06429144B1

公开(公告)日：2002-08-06

申请号：US09473451

申请日：1999-12-28

申请人： Landon B. Vines ,  Felix H. Fujishiro ,  Yu-Pin Han

发明人： Landon B. Vines ,  Felix H. Fujishiro ,  Yu-Pin Han

IPC分类号： H01L21302

CPC分类号： H01L21/31111 ,  H01L21/0206 ,  H01L21/28211 ,  H01L21/28238

摘要： In the manufacture of an integrated circuit, contaminated oxide is replaced by relatively pure oxide using the following steps. First, a partially manufactured integrated circuit is bathed in an aqueous solution of hydrogen peroxide and ammonium hydroxide to oxidize organic materials and weaken bonds of metal contaminants to the integrated circuit substrate. Second, an aqueous rinse removes the oxidized organic materials and metal contaminants. Third, the integrated circuit is bathed in an aqueous solution of hydrogen fluoride and nitric acid. The hydrogen fluroide etches the contaminated oxide; the nitric acid combines with calcium and metal contaminants freed as the oxide is etched. The resulting nitride byproducts are highly soluble and easily removed in the following aqueous rinse. A drying step removes rinse water from the integrated circuit. Finally, an oxide formation step provides a relatively pure oxide layer. In the case of a gate oxide, the method removes a sacrificial oxide in preparation for gate oxide growth. In the case of formation of the submetal dielectric, oxide formation involves an TEOS oxide deposition. A key advantage of the invention is the improved calcium removal due to the nitric acid.

摘要翻译： 在集成电路的制造中，使用以下步骤用相对纯的氧化物代替污染的氧化物。 首先，将部分制造的集成电路沐浴在过氧化氢和氢氧化铵的水溶液中以氧化有机材料并减弱金属污染物与集成电路基板的接合。 第二，水性漂洗去除氧化的有机物质和金属污染物。 第三，将集成电路浸在氟化氢和硝酸的水溶液中。 氢氟酸蚀刻污染的氧化物; 硝酸与钙和金属污染物结合，氧化物被蚀刻掉。 所得的氮化物副产物是高度可溶的并且容易地在下列水性漂洗液中除去。 干燥步骤从集成电路中去除冲洗水。 最后，氧化物形成步骤提供相对纯的氧化物层。 在栅极氧化物的情况下，该方法除去用于栅极氧化物生长的牺牲氧化物。 在形成亚金属电介质的情况下，氧化物形成涉及TEOS氧化物沉积。 本发明的主要优点是由于硝酸而改善的钙去除。

公开(公告)号：US5789795A

公开(公告)日：1998-08-04

申请号：US579824

申请日：1995-12-28

申请人： Ivan Sanchez ,  Yu-Pin Han ,  Miguel A. Delgado ,  Ying-Tsong Loh

发明人： Ivan Sanchez ,  Yu-Pin Han ,  Miguel A. Delgado ,  Ying-Tsong Loh

IPC分类号： H01L23/525 ,  H01L29/00

CPC分类号： H01L23/5252 ,  H01L2924/0002

摘要： An integrated circuit having a semiconductor substrate and an anti-fuse structure formed on the semiconductor substrate. The anti-fuse structure includes a metal-one layer and an anti-fuse layer disposed above the metal-one layer. The anti-fuse layer has a first resistance value when the anti-fuse structure is unprogrammed and a second resistance value lower than the first resistance value when the anti-fuse structure is programmed. There is further provided an etch stop layer disposed above the anti-fuse layer, and an inter-metal oxide layer disposed above the etch stop layer with the inter-metal oxide layer has a via formed therein. Additionally, there is further provided a metal-two layer disposed above the inter-metal oxide layer. In this structure, a portion of the metal-two layer is in electrical contact with the anti-fuse layer through the via in the inter-metal oxide layer.

摘要翻译： 具有形成在半导体衬底上的半导体衬底和抗熔丝结构的集成电路。 反熔丝结构包括金属一层和设置在金属一层上方的抗熔丝层。 当抗熔丝结构未被编程时，抗熔丝层具有第一电阻值，并且当编程防熔丝结构时，抗熔丝层具有低于第一电阻值的第二电阻值。 还提供了设置在反熔丝层上方的蚀刻停止层，并且设置在蚀刻停止层上方的金属间氧化物层与金属间氧化物层在其中形成通孔。 此外，还提供了设置在金属间氧化物层上方的金属二层。 在该结构中，金属二层的一部分通过金属间氧化物层中的通孔与抗熔融层电接触。