公开(公告)号：US06656816B2

公开(公告)日：2003-12-02

申请号：US10142700

申请日：2002-05-10

申请人： Yugo Tomioka

发明人： Yugo Tomioka

IPC分类号： H01L2176

CPC分类号： H01L21/823481 ,  H01L21/76237 ,  H01L21/823493

摘要： A method for manufacturing a semiconductor device enables the formation of a well optimized for a fine MOS transistor and a well formed deep with a relatively low concentration for a high voltage MOS transistor without increasing the number of manufacturing steps. The method for manufacturing a semiconductor device includes the steps of: forming a first ion implantation expendable film and an etching mask film on a first conductive type semiconductor substrate; patterning the etching mask film into a shape of an active and field region; introducing dopant into the substrate; forming a trench groove on the substrate; forming an insulation film in the trench groove; forming a first well; flattening the insulation film; removing the etching mask film; removing the expendable film; forming a second ion implantation expendable film on the substrate; forming a mask pattern; and forming a second well by introducing dopant into the substrate.

摘要翻译： 一种用于制造半导体器件的方法能够形成对于高电压MOS晶体管的精细MOS晶体管和以较低浓度深度形成的阱的良好优化，而不增加制造步骤的数量。 制造半导体器件的方法包括以下步骤：在第一导电型半导体衬底上形成第一离子注入消耗膜和蚀刻掩模膜; 将蚀刻掩模膜图案化成活性和场区域的形状; 将掺杂剂引入衬底中; 在所述基板上形成沟槽; 在沟槽中形成绝缘膜; 形成第一口井; 平整绝缘膜; 去除蚀刻掩模膜; 去除消耗性膜; 在衬底上形成第二离子注入消耗性膜; 形成掩模图案; 以及通过将掺杂剂引入衬底中形成第二阱。

公开(公告)号：US5793081A

公开(公告)日：1998-08-11

申请号：US850449

申请日：1997-05-05

申请人： Yugo Tomioka ,  Yasuo Sato

发明人： Yugo Tomioka ,  Yasuo Sato

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/76 ,  H01L29/788

CPC分类号： H01L27/11519 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A nonvolatile semiconductor storage device in which a composite gate of a floating gate memory cell transistor and a gate electrode of a peripheral MOS transistor are formed in the same lithography process and a manufacturing method thereof. A polycrystalline silicon film and an ONO film are formed on a well region through a gate oxide film and a tunnel oxide film. A polycrystalline silicon film is formed after removing the ONO film in the right region. A floating gate and a control gate of the memory cell transistor and a gate electrode of the select transistor are formed with photoresist as a mask. Thereafter, ions of impurities are implanted and diffused in a transverse direction, thereby to form an impurity diffused layer. With this, since the impurity diffused layer is formed by transverse diffusion of impurities after the tunnel oxide film is formed, it is possible to prevent deterioration of the film quality of the tunnel oxide film.

摘要翻译： 一种非易失性半导体存储器件，其中在相同的光刻工艺中形成浮栅存储单元晶体管的复合栅极和外围MOS晶体管的栅电极及其制造方法。 通过栅极氧化膜和隧道氧化物膜在阱区上形成多晶硅膜和ONO膜。 在去除右区域中的ONO膜之后形成多晶硅膜。 存储单元晶体管的浮栅和控制栅极以及选择晶体管的栅极形成有光致抗蚀剂作为掩模。 此后，杂质的离子注入并在横向扩散，从而形成杂质扩散层。 由此，由于杂质扩散层由形成隧道氧化膜之后的杂质的横向扩散形成，所以可以防止隧道氧化膜的膜质量的劣化。

公开(公告)号：US5596527A

公开(公告)日：1997-01-21

申请号：US387562

申请日：1995-02-13

申请人： Yugo Tomioka ,  Shoichi Iwasa ,  Yasuo Sato ,  Toshio Wada ,  Kenji Anzai

发明人： Yugo Tomioka ,  Shoichi Iwasa ,  Yasuo Sato ,  Toshio Wada ,  Kenji Anzai

IPC分类号： G11C11/56 ,  G11C16/28 ,  G11C11/34

CPC分类号： G11C16/28 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C2211/5621 ,  G11C2211/5634

摘要： An electrically alterable non-volatile memory having a memory cell array including a plurality of memory cells, each memory cell including a transistor having a selected one of a plurality of different threshold voltages; a reference cell array including at least one set of reference cells, each reference cell in the set being set to a different threshold voltage; selection circuitry for selecting one of the memory cells; and a comparing circuitry for comparing a memory current read out of the selected memory cell with each of reference currents read out of the reference cells, sequentially in an order of levels of the threshold voltages set for the reference cells, respectively, thereby outputting data according to such comparison.

摘要翻译： 一种具有包括多个存储单元的存储单元阵列的电可更改的非易失性存储器，每个存储单元包括具有多个不同阈值电压中选择的一个的晶体管; 包括至少一组参考单元的参考单元阵列，所述组中的每个参考单元被设置为不同的阈值电压; 用于选择所述存储器单元之一的选择电路; 以及比较电路，用于将从所选择的存储单元读出的存储器电流与从参考单元读出的参考电流中的每一个依次按照为参考单元设置的阈值电压的电平顺序依次进行比较，从而根据 进行比较。

公开(公告)号：US5355023A

公开(公告)日：1994-10-11

申请号：US68185

申请日：1993-05-28

申请人： Yugo Tomioka ,  Yukihiro Okeda ,  Yasuo Sato

发明人： Yugo Tomioka ,  Yukihiro Okeda ,  Yasuo Sato

IPC分类号： H01L23/522 ,  H01L27/11 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L23/5226 ,  H01L27/1112 ,  H01L2924/0002

摘要： A part of a polycrystalline silicon film forming a grounding line in a memory cell of a high-resistance load type SRAM, located immediately below a contact hole for connection between a polysilicon power supply line part and an aluminum power supply line part, is separated and isolated from the remaining part of the polycrystalline silicon film to form an island-like part. The contact hole extends through an interlayer insulating film below the aluminum power supply line part, the polysilicon power supply line part and another interlayer insulating film above the island part, and reaches the island part, whereby the aluminum power supply line part contacts even the island part through the contact hole. The island part also contacts the polysilicon power supply line part through another contact hole, whereby low-resistance contact can be obtained between the aluminum and polysilicon power supply line parts through the island part. Since the contact hole can be provided at a position above a grounding line, the area of the cell can be reduced. In this case, even when the contact hole reaches the polycrystalline silicon film of the grounding line due to difficulties in its etching control, undesirable short-circuiting can be avoided between the grounding and power supply lines.

摘要翻译： 在位于多晶硅电源线部分和铝电源线部分之间的用于连接的接触孔正下方的高电阻负载型SRAM的存储单元中形成接地线的一部分多晶硅膜被分离， 从多晶硅膜的剩余部分分离形成岛状部分。 接触孔延伸穿过铝电源线部分之下的层间绝缘膜，多晶硅供电线部分和岛部分上方的另一层间绝缘膜，并到达岛部，由此铝电源线部分甚至接触岛 部分通过接触孔。 岛部还通过另一个接触孔与多晶硅供电线部分接触，从而通过岛部分在铝和多晶硅供电线部分之间可以获得低电阻接触。 由于接触孔可以设置在接地线上方的位置，所以可以减小电池的面积。 在这种情况下，即使接触孔由于其蚀刻控制困难而到达接地线的多晶硅膜，也可以避免接地和供电线之间的不期望的短路。

公开(公告)号：US5754464A

公开(公告)日：1998-05-19

申请号：US766505

申请日：1996-12-13

申请人： Yugo Tomioka

发明人： Yugo Tomioka

IPC分类号： H01L21/76 ,  G11C17/12 ,  H01L21/8246 ,  H01L27/112 ,  G11C17/10

CPC分类号： G11C17/12 ,  H01L27/112

摘要： A mask ROM with increased memory capacity is disclosed. Besides MOS transistors each comprising a memory cell, MOS field shield transistors for device isolation, originally provided for electrically isolating the memory cell transistors, are also used as additional memory cells in addition to providing their isolating function. To write data in one of the field shield transistor, the threshold voltage of the field shield transistor is lowered, compared to field shield transistors in other regions. This is done by ion implantation of an n-type impurity into a p-type silicon substrate in a region beneath a gate electrode of the field shield transistor (a channel region). Data is read by judging on/off of the transistors when an intermediate voltage, between a high threshold voltage and a low threshold voltage is applied to a field shield line.

摘要翻译： 公开了具有增加的存储容量的掩模ROM。 除了各自包括存储单元的MOS晶体管之外，还提供用于电隔离存储单元晶体管的用于器件隔离的MOS场屏蔽晶体管，除了提供它们的隔离功能之外还用作附加存储器单元。 为了在场屏蔽晶体管之一中写入数据，与其他区域中的场屏蔽晶体管相比，场屏蔽晶体管的阈值电压降低。 这通过在场屏蔽晶体管（沟道区域）的栅电极下方的区域中将n型杂质离子注入到p型硅衬底中来完成。 当将高阈值电压和低阈值电压之间的中间电压施加到场屏蔽线时，通过判断晶体管的开/关来读取数据。

公开(公告)号：US5343062A

公开(公告)日：1994-08-30

申请号：US67101

申请日：1993-05-26

申请人： Yugo Tomioka

发明人： Yugo Tomioka

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/92 ,  H01L29/68 ,  H01L29/78

CPC分类号： H01L28/75 ,  H01L27/10852 ,  H01L27/10811

摘要： A semiconductor memory having a memory cell including a stacked capacitor in which a lower electrode contacting one of two diffusion regions of an access transistor is formed in the form of two layers. It is preferable that impurities having a smaller diffusion coefficient, or arsenic is introduced into a first layer of the lower electrode contacting the diffusion region, and impurities having a larger diffusion coefficient, or phosphorus is introduced into a second layer of the lower electrode contacting capacitor dielectric film. Since a diffusion coefficient of arsenic is small, it is possible to prevent the junction of the diffusion region from becoming deep and on the other hand since phosphorus is introduced into the second polycrystalline Si film contacting the capacitor dielectric film, it is possible to prevent the degradation of the film quality of the capacitor dielectric film.

摘要翻译： 一种半导体存储器，具有包括层叠电容器的存储单元，其中以两层形式形成接触晶体管的两个扩散区域中的一个的下电极。 优选将扩散系数较小的杂质或砷引入到与扩散区接触的下部电极的第一层，扩散系数较大的杂质或磷被引入下部电极接触电容器的第二层 电介质膜。 由于砷的扩散系数小，可以防止扩散区域的接合变深，另一方面由于将磷引入到与电容器电介质膜接触的第二多晶Si膜中，因此可以防止 电容器介质膜的质量降低。

公开(公告)号：US5796140A

公开(公告)日：1998-08-18

申请号：US517022

申请日：1995-08-21

申请人： Yugo Tomioka

发明人： Yugo Tomioka

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324

摘要： A nonvolatile semiconductor memory device including a plurality of memory cells, and a method of making this memory device. The nonvolatile semiconductor memory device includes: a semiconductor substrate; an element-isolation structure formed in a surface of the semiconductor substrate and having at least two linear portions extending in a longitudinal direction to define at least one element region between them; and at least one of the memory cells formed in the element region and including: a pair of impurity diffusion layers formed in the surface of said semiconductor substrate along each of the linear portions and a floating gate of a conductive material formed in the element region so as to extend in a lateral direction crossing the longitudinal direction and to bridge the two linear portions, the floating gate including at least a first portion formed on the surface of the semiconductor substrate through a tunnel oxide film and a second portion formed on the surface of the semiconductor substrate through a gate oxide film so as to cover the first portion, the tunnel oxide film having a thickness smaller than that of the gate oxide film, wherein the first portion overlaps through the tunnel oxide film with one of the impurity diffusion layers at an overlapping area extending in the longitudinal direction and having a width equal to or less than 0.18 .mu.m measured in the lateral direction.

摘要翻译： 包括多个存储单元的非易失性半导体存储器件以及制造该存储器件的方法。 非易失性半导体存储器件包括：半导体衬底; 元件隔离结构，其形成在所述半导体衬底的表面中并且具有至少两个在纵向方向上延伸的直线部分，以在它们之间限定至少一个元件区域; 以及形成在元件区域中的至少一个存储单元，包括：沿着每个线性部分形成在所述半导体衬底的表面中的一对杂质扩散层和形成在元件区域中的导电材料的浮置栅极，因此 为了沿着与纵向交叉的横向方向延伸并且桥接两个线性部分，浮动栅极包括通过隧道氧化物膜形成在半导体衬底的表面上的至少第一部分和形成在半导体衬底的表面上的第二部分 所述半导体衬底通过栅极氧化膜覆盖所述第一部分，所述隧道氧化物膜的厚度小于所述栅极氧化物膜的厚度，其中所述第一部分与所述隧道氧化物膜重叠，其中所述杂质扩散层之一位于 沿纵向方向延伸并且具有等于或小于横向测量的0.18μm的宽度的重叠区域。

公开(公告)号：US5668756A

公开(公告)日：1997-09-16

申请号：US576086

申请日：1995-12-21

申请人： Yugo Tomioka

发明人： Yugo Tomioka

IPC分类号： G11C11/56 ,  G11C11/34

CPC分类号： G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642

摘要： A non-volatile semiconductor memory unit comprises a memory cell having a semiconductor substrate, a control gate formed over the semiconductor substrate, an electric charge accumulative layer formed between the semiconductor substrate and the control gate, and a source and drain, both formed in the semiconductor substrate. The memory cell stores N-valued data (N being an integer more than 3) by accumulating an electric charge in the electric charge accumulative layer. A detector is provided for detecting a storage state before data rewrite of the memory cell. A comparison circuit compares the storage state before data rewrite, with a storage state after data rewrite to produce a difference therebetween. A rewrite circuit is included for rewriting the storage state of the memory cell by applying N-1 levels of predetermined voltages to the source, the drain and control gate of the memory cell, respectively, in accordance with the produced difference.

摘要翻译： 非易失性半导体存储器单元包括具有半导体衬底的存储单元，形成在半导体衬底上的控制栅极，形成在半导体衬底和控制栅极之间的电荷累积层以及源极和漏极，二者形成在 半导体衬底。 存储单元通过在电荷累积层中积累电荷来存储N值数据（N是大于3的整数）。 提供检测器，用于在存储单元的数据重写之前检测存储状态。 比较电路将数据重写之前的存储状态与数据重写之后的存储状态进行比较，以在它们之间产生差异。 包括重写电路，用于根据产生的差分，分别对存储单元的源极，漏极和控制栅极施加N-1级的预定电压，来重写存储单元的存储状态。

公开(公告)号：US5640032A

公开(公告)日：1997-06-17

申请号：US525264

申请日：1995-09-07

申请人： Yugo Tomioka

发明人： Yugo Tomioka

IPC分类号： H01L27/115 ,  H01L29/423 ,  H01L29/68

CPC分类号： H01L27/115 ,  H01L29/42324

摘要： A non-volatile semiconductor memory device comprises a semiconductor substrate, a shield gate electrode formed over a device isolation region of the semiconductor substrate through a shield gate insulating film, a floating gate electrode formed over a device region of the semiconductor substrate through a tunnel insulating film, the device region lying adjacent to the device isolation region and a part of the floating gate electrode overlapping the device isolation region so as to form a gap region therebetween, and a control gate electrode formed over the floating gate electrode through an oxide/nitride/oxide (ONO) film and formed over the shield gate electrode through a shield cap insulating film such that a part of the control gate electrode extends into the gap region.

摘要翻译： 非易失性半导体存储器件包括半导体衬底，通过屏蔽栅极绝缘膜在半导体衬底的器件隔离区上形成的屏蔽栅电极，通过隧道绝缘形成在半导体衬底的器件区域上方的浮栅电极 膜，器件区域位于器件隔离区域附近，并且浮置栅电极的一部分与器件隔离区域重叠以便在其间形成间隙区域;以及控制栅电极，其通过氧化物/氮化物形成在浮栅上 /氧化物（ONO）膜，并通过屏蔽帽绝缘膜形成在屏蔽栅电极上，使得控制栅电极的一部分延伸到间隙区域中。

公开(公告)号：US5418743A

公开(公告)日：1995-05-23

申请号：US161508

申请日：1993-12-06

申请人： Yugo Tomioka ,  Shoichi Iwasa ,  Yasuo Sato ,  Toshio Wada ,  Kenji Anzai

发明人： Yugo Tomioka ,  Shoichi Iwasa ,  Yasuo Sato ,  Toshio Wada ,  Kenji Anzai

IPC分类号： G11C11/56 ,  G11C16/28 ,  G11C11/40

CPC分类号： G11C16/28 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C2211/5621 ,  G11C2211/5634

摘要： A method of using a non-volatile semiconductor memory comprising a plurality of row and column lines, a plurality of memory cells disposed at intersections of the row and column lines and a plurality of reference cells disposed on each of the row lines. Each memory cell includes an MOS transistor having a substrate, a spaced-apart drain and source formed on one surface of the substrate, a channel region between the drain and source and a lamination of a tunnel insulating film, a floating gate, an interlayer insulating film and a control gate formed in that order on the channel region. Each reference cell has the same electrical characteristic as the memory cell, with the method including:(1) when writing data into each of the memory cells:(a) presetting threshold voltages of the MOS transistor to correspond to at least three different data to be stored in each of the memory cells; and(b) applying to the control gate and the drain the MOS transistor included in a selected memory cell, respectively, a selected high voltage, and a voltage determined according to one of the preset threshold voltages corresponding to one of the at least three different data to be stored while maintaining the source in a floating voltage condition; and(2) when reading out data of the memory cell:(a) selecting the reference cells disposed on one of the row lines on which a selected one of the memory cells is disposed; and(b) setting threshold voltages of the selected reference cells at values determined based on the preset threshold voltages.

摘要翻译： 一种使用非易失性半导体存储器的方法，所述非易失性半导体存储器包括多行行和列线，多个存储单元设置在行和列线的交点处，以及多个参考单元设置在每条行线上。 每个存储单元包括MOS晶体管，其具有衬底，形成在衬底的一个表面上的间隔开的漏极和源极，漏极和源极之间的沟道区域以及隧道绝缘膜，浮动栅极，层间绝缘层 膜和在该通道区上依次形成的控制栅。 每个参考单元具有与存储单元相同的电特性，其方法包括：（1）当将数据写入每个存储单元时：（a）将MOS晶体管的阈值电压预设为对应于至少三个不同的数据， 存储在每个存储单元中; 以及（b）分别向所述控制栅极和所述漏极施加包括在所选择的存储单元中的所述MOS晶体管选择的高电压，以及根据与所述至少三个不同的一个中的一个不同的预定阈值电压之一确定的电压 在将源保持在浮动电压状态的同时存储的数据; （2）当读出存储单元的数据时：（a）选择布置在其上布置所选存储单元的行行之一上的参考单元; 和（b）将所选参考单元的阈值电压设置在基于预设阈值电压确定的值。