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    Circuit analyzing method and circuit analyzing device
    1.
    发明申请
    Circuit analyzing method and circuit analyzing device 审中-公开
    电路分析方法和电路分析装置

    公开(公告)号：US20050268261A1

    公开(公告)日：2005-12-01

    申请号：US11136663

    申请日：2005-05-25

    申请人： Kaori Hatakeyama ,  Yukihiro Sasagawa

    发明人： Kaori Hatakeyama ,  Yukihiro Sasagawa

    IPC分类号： G06F17/50 ,  G01R27/26 ,  G06F9/45 ,  H01L21/82

    CPC分类号： G06F17/5081

    摘要： A circuit analyzing device according to the present invention comprises a capacitance value extracting unit for extracting a capacitance value of a functional element from design information including layout information of a semiconductor integrated circuit and a capacitance value outputting unit for displaying the functional element in the semiconductor integrated circuit or a functional-element connecting wiring linked to the functional element on a design drawing including the layout information of the semiconductor integrated circuit in a discriminating manner in accordance with the capacitance value of the functional element, or comprises a per-attribute capacitance value operation unit for executing an operation of the capacitance value per attribute based on a functional-element attribute library in which attribute information of the functional element in the semiconductor integrated circuit is stored and the capacitance value of the functional element and a per-attribute capacitance value outputting unit for outputting the capacitance value per attribute calculated by the per-attribute capacitance value operation unit.

    摘要翻译： 根据本发明的电路分析装置包括电容值提取单元，用于从包括半导体集成电路的布局信息的设计信息和用于在半导体集成中显示功能元件的电容值输出单元提取功能元件的电容值 电路或功能元件连接到功能元件的功能元件的设计图，包括根据功能元件的电容值的鉴别方式的半导体集成电路的布局信息，或者包括每属性电容值操作 基于存储半导体集成电路中的功能元件的属性信息的功能元素属性库，执行每个属性的电容值的操作的单元，以及功能元件的电容值和每属性电容 平均值输出单元，用于输出由每个属性电容值操作单元计算的每个属性的电容值。

    Neural network system
    2.
    发明授权
    Neural network system 有权
    神经网络系统

    公开(公告)号：US08694451B2

    公开(公告)日：2014-04-08

    申请号：US13233196

    申请日：2011-09-15

    申请人： Yukihiro Sasagawa

    发明人： Yukihiro Sasagawa

    IPC分类号： G06F15/18 ,  G06N3/08

    CPC分类号： G06N3/063

    摘要： A neural network system that can minimize circuit resources for constituting a self-learning mechanism and be reconfigured into network configurations suitable for various purposes includes a neural network engine that operates in a first and a second operation mode and performs an operation representing a characteristic determined by setting network configuration information and weight information with respect to the network configuration, and a von Neumann-type microprocessor that is connected to the neural network engine and performs a cooperative operation in accordance with the first or the second operation mode together with the neural network engine. The von Neumann-type microprocessor recalculates the weight information or remakes the configuration information as a cooperative operation according to the first operation mode, and sets or updates the configuration information or the weight information set in the neural network engine, as a cooperative operation according to the second operation mode.

    摘要翻译： 一种神经网络系统，其可以将用于构成自学习机制的电路资源最小化并被重新配置为适合于各种目的的网络配置的神经网络系统包括在第一和第二操作模式中操作的神经网络引擎，并执行表示由 设置关于网络配置的网络配置信息和权重信息，以及连接到神经网络引擎并根据第一或第二操作模式与神经网络引擎执行协作操作的冯诺依曼型微处理器 。 冯·诺依曼型微处理器根据第一操作模式重新计算权重信息或重新配置配置信息作为协作操作，并且根据第一操作模式将配置信息或设置在神经网络引擎中的权重信息设置或更新为协作操作 第二种操作模式。

    Pulse synthesis circuit
    5.
    发明授权
    Pulse synthesis circuit 有权
    脉冲合成电路

    公开(公告)号：US07920002B2

    公开(公告)日：2011-04-05

    申请号：US12133901

    申请日：2008-06-05

    申请人： Shiro Sakiyama ,  Yusuke Tokunaga ,  Shiro Dosho ,  Akinori Matsumoto ,  Takashi Morie ,  Kazuaki Sogawa ,  Yukihiro Sasagawa ,  Masaya Sumita

    发明人： Shiro Sakiyama ,  Yusuke Tokunaga ,  Shiro Dosho ,  Akinori Matsumoto ,  Takashi Morie ,  Kazuaki Sogawa ,  Yukihiro Sasagawa ,  Masaya Sumita

    IPC分类号： H03K5/01

    CPC分类号： H03K5/00006 ,  H03K5/13

    摘要： A high-level period of each of n first pulse signals partially or wholly overlaps a period during which all of n second pulse signals are at the low level. A high-level period of each of the n second pulse signals partially or wholly overlaps a period during which all of the n first pulse signals are at the low level. Each of n first drive transistors includes a source connected to a ground node, a drain connected to a first node, and a gate receiving a corresponding one of the first pulse signals. Each of n second drive transistors includes a source connected to the ground node, a drain connected to a second node, and a gate receiving a corresponding one of the second pulse signals. A current mirror circuit allows a current corresponding to a current flowing through the second node to flow through the first node.

    摘要翻译： n个第一脉冲信号中的每一个的高电平周期部分或全部与在所有n个第二脉冲信号都处于低电平的期间重叠。 n个第二脉冲信号中的每一个的高电平周期部分地或完全地重叠在所有n个第一脉冲信号处于低电平的时段。 n个第一驱动晶体管中的每一个包括连接到接地节点的源极，连接到第一节点的漏极以及接收相应的一个第一脉冲信号的栅极。 n个第二驱动晶体管中的每一个包括连接到接地节点的源极，连接到第二节点的漏极和接收相应的一个第二脉冲信号的栅极。 电流镜电路允许对应于流过第二节点的电流的电流流过第一节点。

    Dynamic circuit
    6.
    发明授权
    Dynamic circuit 有权
    动态电路

    公开(公告)号：US07830178B2

    公开(公告)日：2010-11-09

    申请号：US11699422

    申请日：2007-01-30

    申请人： Yukihiro Sasagawa

    发明人： Yukihiro Sasagawa

    IPC分类号： H03K19/096

    CPC分类号： H03K19/0966

    摘要： The dynamic circuit includes: a dynamic node; an evaluation circuit for changing the charged state of the dynamic node according to a result of logic evaluation for a plurality of input signals; a control circuit for outputting a control signal of which the logic level changes according to the result of logic evaluation performed by a replica of the evaluation circuit; and an initialization circuit for receiving the control signal from the control circuit and an external control signal, to control start and stop of initialization of the dynamic node according to the control signals.

    摘要翻译： 动态电路包括：动态节点; 评估电路，用于根据多个输入信号的逻辑评估结果来改变动态节点的充电状态; 控制电路，用于输出逻辑电平根据由评估电路的副本执行的逻辑评估结果而改变的控制信号; 以及用于从控制电路接收控制信号的初始化电路和外部控制信号，以根据控制信号控制动态节点的初始化的开始和停止。

    Event-driven logic circuit
    7.
    发明授权
    Event-driven logic circuit 有权
    事件驱动逻辑电路

    公开(公告)号：US07285985B2

    公开(公告)日：2007-10-23

    申请号：US11195614

    申请日：2005-08-03

    申请人： Yukihiro Sasagawa ,  Atsushi Takahata

    发明人： Yukihiro Sasagawa ,  Atsushi Takahata

    IPC分类号： H03K19/00

    CPC分类号： H03K19/0963

    摘要： A logic circuit comprises: an event generator for detecting a variation in data output from a signal source to generate an event which indicates the variation of the data; a plurality of propagation elements for propagating the event in a chained fashion; and a plurality of evaluation elements for evaluating data received at a first stage from the signal source to propagate a result of the evaluation in a chained fashion. When receiving the event, each of the plurality of evaluation elements evaluates the data input to the evaluation element.

    摘要翻译： 逻辑电路包括：事件发生器，用于检测从信号源输出的数据的变化，以产生指示数据变化的事件; 用于以链式方式传播事件的多个传播元件; 以及多个评估元件，用于评估从信号源在第一阶段接收到的数据，以链式方式传播评估结果。 当接收到事件时，多个评估元件中的每一个评估输入到评估元件的数据。

    PULSE SYNTHESIS CIRCUIT
    9.
    发明申请
    PULSE SYNTHESIS CIRCUIT 有权
    脉冲合成电路

    公开(公告)号：US20080315933A1

    公开(公告)日：2008-12-25

    申请号：US12133901

    申请日：2008-06-05

    申请人： Shiro Sakiyama ,  Yusuke Tokunaga ,  Shiro Dosho ,  Akinori Matsumoto ,  Takashi Morie ,  Kazuaki Sogawa ,  Yukihiro Sasagawa ,  Masaya Sumita

    发明人： Shiro Sakiyama ,  Yusuke Tokunaga ,  Shiro Dosho ,  Akinori Matsumoto ,  Takashi Morie ,  Kazuaki Sogawa ,  Yukihiro Sasagawa ,  Masaya Sumita

    IPC分类号： H03K3/00

    CPC分类号： H03K5/00006 ,  H03K5/13

    摘要： A high-level period of each of n first pulse signals partially or wholly overlaps a period during which all of n second pulse signals are at the low level. A high-level period of each of the n second pulse signals partially or wholly overlaps a period during which all of the n first pulse signals are at the low level. Each of n first drive transistors includes a source connected to a ground node, a drain connected to a first node, and a gate receiving a corresponding one of the first pulse signals. Each of n second drive transistors includes a source connected to the ground node, a drain connected to a second node, and a gate receiving a corresponding one of the second pulse signals. A current mirror circuit allows a current corresponding to a current flowing through the second node to flow through the first node.

    摘要翻译： n个第一脉冲信号中的每一个的高电平周期部分或全部与在所有n个第二脉冲信号都处于低电平的期间重叠。 n个第二脉冲信号中的每一个的高电平周期部分地或完全地重叠在所有n个第一脉冲信号处于低电平的时段。 n个第一驱动晶体管中的每一个包括连接到接地节点的源极，连接到第一节点的漏极以及接收相应的一个第一脉冲信号的栅极。 n个第二驱动晶体管中的每一个包括连接到接地节点的源极，连接到第二节点的漏极和接收相应的一个第二脉冲信号的栅极。 电流镜电路允许对应于流过第二节点的电流的电流流过第一节点。

    Low power operation control unit and program optimizing method
    10.
    发明授权
    Low power operation control unit and program optimizing method 有权
    低功率运行控制单元和程序优化方法

    公开(公告)号：US07430678B2

    公开(公告)日：2008-09-30

    申请号：US11500456

    申请日：2006-08-08

    申请人： Yukihiro Sasagawa

    发明人： Yukihiro Sasagawa

    IPC分类号： G06F1/26

    CPC分类号： G06F9/30083 ,  G06F1/3203 ,  G06F1/3243 ,  G06F1/329 ,  G06F9/30072 ,  G06F9/30145 ,  G06F9/30189 ,  Y02D10/152 ,  Y02D10/24 ,  Y02D50/20

    摘要： An objective is to perform a low power operation of a microprocessor on the pipeline stage of an instruction decode and a preceding pipeline stage without the necessity for increasing a circuit size or decoding time. An instruction code of each program for performing an instruction includes a first instruction set, which includes a flag for specifying predicate (301), and one or more second instruction sets including control specification information (302). A low power operation of each control circuit is performed for each instruction according to the instruction execution control function. Thus, without the necessity for increasing a circuit size or decoding time, it is possible to control the pipeline stage of an instruction decode and a preceding pipeline stage, achieving a low power operation of the microprocessor.

    摘要翻译： 目的是在指令解码和前一流水线级的流水线级上执行微处理器的低功率操作，而不需要增加电路尺寸或解码时间。 用于执行指令的每个程序的指令代码包括包括用于指定谓词（301）的标志的第一指令集和包括控制指定信息（302）的一个或多个第二指令集。 根据指令执行控制功能，对每个指令执行每个控制电路的低功率操作。 因此，不需要增加电路尺寸或解码时间，可以控制指令译码和前一流水线级的流水线级，实现微处理器的低功率操作。