公开(公告)号：US20140125381A1

公开(公告)日：2014-05-08

申请号：US13668705

申请日：2012-11-05

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Russell Schreiber ,  John Wuu ,  Keith Kasprak

IPC: H03K19/00 ,  G06F17/50

CPC classification number: G06F17/50 ,  G06F13/1689 ,  G06F13/4291 ,  G06F17/5045 ,  G06F2217/62 ,  H03K19/00 ,  H05K3/00

Abstract: An integrated circuit (IC) generates clock delay control signals based on its operational voltage level. The clock delay control signals are routed to corresponding clock gating logic that controls the synchronous capturing of the outputs of corresponding signal paths. The clock gating logic delays the clock signal used by the corresponding flip-flop in response to an assertion of the corresponding received clock delay control. Thus, the clock signal used to capture the outputs of certain signal paths may be delayed under certain voltage conditions. This selective clock path delay for different signal paths enables the IC to use a higher clock frequency, or more reliably latch the path outputs at a certain clock frequency, even though different signal paths may exhibit different relative path delays under different operating voltage conditions.

Abstract translation: 集成电路（IC）根据其工作电压电平产生时钟延迟控制信号。 时钟延迟控制信号被路由到对应的时钟门控逻辑，其控制相应信号路径的输出的同步捕获。 响应于对应的接收时钟延迟控制的断言，时钟门控逻辑延迟由相应触发器使用的时钟信号。 因此，用于捕获某些信号路径的输出的时钟信号可能在某些电压条件下被延迟。 即使在不同的工作电压条件下不同的信号路径可能表现出不同的相对路径延迟，不同信号路径的这种选择性时钟路径延迟使得IC能够使用更高的时钟频率，或者更可靠地锁定一定时钟频率的路径输出。

公开(公告)号：US20190034572A1

公开(公告)日：2019-01-31

申请号：US15663132

申请日：2017-07-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Keith Kasprak ,  Patrick W. Shaw

IPC: G06F17/50 ,  H01L27/02

Abstract: Systems, apparatuses, and methods for efficiently floor planning a semiconductor chip are disclosed. Within either the processor or the memory of a computing system, each of a first block and a neighboring second block has a same height. A first metal track plan for the first block is unaligned with respect to a second metal track plan for the second block. An offset for moving each track of the second metal plan to align with a track of the first metal track plan is determined where the offset is a fraction of the height. The placement of the second block is shifted by the offset with respect to the first block. The shifted placement of the second block allows the first metal track plan for the first block to use a unidirectional pattern across the first block and the second block.

公开(公告)号：US10747931B2

公开(公告)日：2020-08-18

申请号：US15663132

申请日：2017-07-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Keith Kasprak ,  Patrick W. Shaw

IPC: G06F30/392 ,  H01L27/02 ,  G06F30/394 ,  G06F30/398 ,  H01L27/11

Abstract: Systems, apparatuses, and methods for efficiently floor planning a semiconductor chip are disclosed. Within either the processor or the memory of a computing system, each of a first block and a neighboring second block has a same height. A first metal track plan for the first block is unaligned with respect to a second metal track plan for the second block. An offset for moving each track of the second metal plan to align with a track of the first metal track plan is determined where the offset is a fraction of the height. The placement of the second block is shifted by the offset with respect to the first block. The shifted placement of the second block allows the first metal track plan for the first block to use a unidirectional pattern across the first block and the second block.

公开(公告)号：US10043572B1

公开(公告)日：2018-08-07

申请号：US15663096

申请日：2017-07-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell Schreiber ,  John J. Wuu ,  Keith Kasprak

IPC: G11C11/40 ,  G11C11/419 ,  G11C11/418 ,  G11C5/14 ,  G11C5/06

Abstract: A system and method for providing efficient power, performance and stability tradeoffs of memory accesses are described. A computing system uses a memory for storing data, and a processing unit, which generates access request. The memory stores data and includes a dummy cell between a first region and a second region. The first region and the second region operate with at least one of two operating states such as an awake state and a sleep state. The dummy cell uses two ground connections to support two separate ground references. In one example, a first ground reference is zero volts and a second ground reference is a floating node. In another example, the first ground reference is a value shared by one of the two regions and the second ground reference is the floating node.

公开(公告)号：US09053257B2

公开(公告)日：2015-06-09

申请号：US13668705

申请日：2012-11-05

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell Schreiber ,  John Wuu ,  Keith Kasprak

IPC: H03K19/00 ,  G06F17/50 ,  G06F13/16 ,  H05K3/00 ,  G06F13/42

CPC classification number: G06F17/50 ,  G06F13/1689 ,  G06F13/4291 ,  G06F17/5045 ,  G06F2217/62 ,  H03K19/00 ,  H05K3/00

Abstract: An integrated circuit (IC) generates clock delay control signals based on its operational voltage level. The clock delay control signals are routed to corresponding clock gating logic that controls the synchronous capturing of the outputs of corresponding signal paths. The clock gating logic delays the clock signal used by the corresponding flip-flop in response to an assertion of the corresponding received clock delay control. Thus, the clock signal used to capture the outputs of certain signal paths may be delayed under certain voltage conditions. This selective clock path delay for different signal paths enables the IC to use a higher clock frequency, or more reliably latch the path outputs at a certain clock frequency, even though different signal paths may exhibit different relative path delays under different operating voltage conditions.

Abstract translation: 集成电路（IC）根据其工作电压电平产生时钟延迟控制信号。 时钟延迟控制信号被路由到对应的时钟门控逻辑，其控制相应信号路径的输出的同步捕获。 响应于对应的接收时钟延迟控制的断言，时钟门控逻辑延迟由相应触发器使用的时钟信号。 因此，用于捕获某些信号路径的输出的时钟信号可能在某些电压条件下被延迟。 即使在不同的工作电压条件下不同的信号路径可能表现出不同的相对路径延迟，不同信号路径的这种选择性时钟路径延迟使得IC能够使用更高的时钟频率，或者更可靠地锁定一定时钟频率的路径输出。