-
公开(公告)号：US10903204B2
公开(公告)日：2021-01-26
申请号：US16043658
申请日：2018-07-24
发明人： Che-Hao Chuang , Chih-Ting Yeh , Kun-Hsien Lin
IPC分类号： H01L27/02 , H01L29/06 , H01L29/861
摘要： A lateral transient voltage suppressor device is provided, comprising a doped substrate, a lateral clamping structure disposed on the doped substrate, a buried doped layer disposed between the doped substrate and the lateral clamping structure for isolation, at least one diode module, and at least one trench arranged in the doped substrate, having a depth not less than that of the buried doped layer, and being disposed between the lateral clamping structure and the at least one diode module for electrical isolation. The doped substrate and the buried doped layer have opposite conductivity types such that the doped substrate is electrically floating. The buried doped layer can be further disposed to separate the diode module from the doped substrate. By employing the proposed invention, the lateral transient voltage suppressor device is advantageous of maintaining both a lower clamping voltage as well as a reduced dynamic resistance.
-
公开(公告)号：US11508853B2
公开(公告)日：2022-11-22
申请号：US16940789
申请日：2020-07-28
发明人： Chih-Ting Yeh , Sung-Chih Huang , Che-Hao Chuang
IPC分类号： H01L29/861 , H01L29/06 , H01L29/08
摘要： A vertical bipolar transistor device includes a heavily-doped semiconductor substrate, a first semiconductor epitaxial layer, at least one doped well, an isolation structure, and an external conductor. The heavily-doped semiconductor substrate and the doped well have a first conductivity type, and the first semiconductor epitaxial layer has a second conductivity type. The first semiconductor epitaxial layer is formed on the heavily-doped semiconductor substrate. The doped well is formed in the first semiconductor epitaxial layer. The isolation structure, formed in the heavily-doped semiconductor substrate and the first semiconductor epitaxial layer, surrounds the first semiconductor epitaxial layer and the at least one doped well. The external conductor is arranged outside the first semiconductor epitaxial layer and the doped well and electrically connected to the first semiconductor epitaxial layer and the doped well.
-
公开(公告)号：US10388647B1
公开(公告)日：2019-08-20
申请号：US16105318
申请日：2018-08-20
发明人： Kun-Hsien Lin , Zi-Ping Chen , Che-Hao Chuang
IPC分类号： H01L29/74 , H01L31/111 , H01L27/02 , H01L23/528 , H01L27/06 , H01L29/861 , H01L29/735
摘要： An improved transient voltage suppression device includes a semiconductor substrate, a transient voltage suppressor, at least one first diode, at least one conductive pad, and at least one second diode. The transient voltage suppressor has an N-type heavily-doped clamping area. The first anode of the first diode is electrically connected to the N-type heavily-doped clamping area. The conductive pad is electrically connected to the first cathode of the first diode. The second anode of the second diode is electrically connected to the conductive pad and the second cathode of the second diode is electrically connected to the transient voltage suppressor. The first anode is closer to the N-type heavily-doped clamping area rather than the conductive pad. The conductive pad is closer to the N-type heavily-doped clamping area rather than the second anode.
-
公开(公告)号：US09224702B2
公开(公告)日：2015-12-29
申请号：US14104251
申请日：2013-12-12
发明人： Ming-Dou Ker , Che-Hao Chuang
CPC分类号： H01L23/60 , H01L23/66 , H01L24/16 , H01L24/17 , H01L25/0655 , H01L25/0657 , H01L2224/16 , H01L2224/16146 , H01L2224/16227
摘要： A three-dimension (3D) integrated circuit (IC) package is disclosed. The 3D IC package has a package substrate having a surface. At least one integrated circuit (IC) chip with or without suppressing a transient voltage and at least one transient voltage suppressor (TVS) chip are arranged on the surface of the substrate and electrically connected with each other. The IC chip is independent from the TVS chip. The IC chip and the TVS chip stacked on each other are arranged on the package substrate. Alternatively, the IC chip and the TVS chip are together arranged on an interposer formed on the package substrate.
摘要翻译： 公开了一种三维（3D）集成电路（IC）封装。 3D IC封装具有具有表面的封装衬底。 具有或不抑制瞬态电压的至少一个集成电路（IC）芯片和至少一个瞬态电压抑制器（TVS）芯片布置在基板的表面上并彼此电连接。 IC芯片独立于TVS芯片。 彼此堆叠的IC芯片和TVS芯片布置在封装基板上。 或者，IC芯片和TVS芯片一起排列在形成在封装基板上的插入件上。
-
公开(公告)号：US11271099B2
公开(公告)日：2022-03-08
申请号：US16940750
申请日：2020-07-28
发明人： Chih-Ting Yeh , Sung-Chih Huang , Che-Hao Chuang
IPC分类号： H01L29/732 , H01L27/02
摘要： A vertical bipolar transistor device is disclosed. The vertical bipolar transistor device includes a heavily-doped semiconductor substrate, a first semiconductor epitaxial layer, at least one first doped well, and an external conductor. The heavily-doped semiconductor substrate and the first doped well have a first conductivity type. The first semiconductor epitaxial layer has a second conductivity type. The first semiconductor epitaxial layer is formed on the heavily-doped semiconductor substrate. The first doped well is formed in the first semiconductor epitaxial layer. The external conductor is arranged outside the heavily-doped semiconductor substrate and the first semiconductor epitaxial layer and electrically connected to the heavily-doped semiconductor substrate and the first semiconductor epitaxial layer.
-
公开(公告)号：US10355144B1
公开(公告)日：2019-07-16
申请号：US16042130
申请日：2018-07-23
发明人： Chih-Ting Yeh , Sung-Chih Huang , Che-Hao Chuang
IPC分类号： H01L29/866 , H01L23/34 , H01L27/02 , H01L29/06 , H01L29/66
摘要： A heat-dissipating Zener diode includes a heavily-doped semiconductor substrate having a first conductivity type, a first epitaxial layer having the first conductivity type, a first heavily-doped area having a second conductivity type, a second epitaxial layer, and a second heavily-doped area having the second conductivity type or the first conductivity type. The first epitaxial layer is formed on the heavily-doped semiconductor substrate. The first heavily-doped area is formed in the first epitaxial layer and spaced from the heavily-doped semiconductor substrate. The second epitaxial layer is formed on the first epitaxial layer and penetrated with a first doped area, and the first doped area has the second conductivity type and contacts the first heavily-doped area. The second heavily-doped area is formed in the first doped area.
-
公开(公告)号：US10041995B2
公开(公告)日：2018-08-07
申请号：US14597413
申请日：2015-01-15
发明人： Ming-Dou Ker , Che-Hao Chuang
IPC分类号： G01R31/20 , H01L23/495 , G01R31/28
CPC分类号： G01R31/2893 , H01L2224/49171
摘要： In a test method for eliminating electrostatic charges, at least one test process is firstly performed by a test equipment comprising a tester and a platform, and electrostatic charges are generated on the test equipment in the test process. In the test process, the tester contacts and tests at least one tested integrated circuit (IC) on a test area of the platform, and then the tested IC is removed from the tester and the test area. Next, a conduction device which is grounded is moved to the test area, so that the tester contacts the conduction device to discharge the electrostatic charges to ground. Next, the conduction device is removed from the tester and the test area. Finally, the method returns to the test process to test the next tested IC.
-
公开(公告)号：US11509133B2
公开(公告)日：2022-11-22
申请号：US17132389
申请日：2020-12-23
发明人： Chih-Ting Yeh , Sung-Chih Huang , Che-Hao Chuang
摘要： A transient voltage suppression device includes at least one diode string, a power clamp device, at least one first bypass diode, and at least two second bypass diodes. The diode string is coupled between a power terminal and a common bus and coupled to an input output (I/O) port. The power clamp device is coupled between the power terminal and the common bus. The first bypass diode is coupled between the common bus and a ground terminal. The second bypass diodes are coupled in series, coupled between the common bus and the ground terminal, and coupled to the first bypass diode in reverse parallel. Alternatively, the first bypass diode and the second bypass diodes are replaced with at least one bi-directional electrostatic discharge (ESD) device.
-
公开(公告)号：US11476243B2
公开(公告)日：2022-10-18
申请号：US17335744
申请日：2021-06-01
发明人： Chih-Ting Yeh , Che-Hao Chuang
摘要： A floating base silicon controlled rectifier is provided, which at least comprises a first conductivity type layer; a second conductivity type well formed in the first conductivity type layer; a first conductivity type heavily doped region coupled to a first node and formed in the second conductivity type well; and a second conductivity type heavily doped region coupled to a second node and formed in the first conductivity type layer. The first conductivity type and the second conductivity type are opposite. When the first conductivity type is N type, the second conductivity type is P type. Alternatively, when the first conductivity type is P type, the second conductivity type is N type. By employing the proposed present invention, the floating base silicon controlled rectifier acts as a forward diode, and an input capacitance can be greatly reduced.
-
公开(公告)号：US11056481B2
公开(公告)日：2021-07-06
申请号：US16101953
申请日：2018-08-13
发明人： Chih-Ting Yeh , Che-Hao Chuang
摘要： A floating base silicon controlled rectifier is provided, which at least comprises a first conductivity type layer; a second conductivity type well formed in the first conductivity type layer; a first conductivity type heavily doped region coupled to a first node and formed in the second conductivity type well; and a second conductivity type heavily doped region coupled to a second node and formed in the first conductivity type layer. The first conductivity type and the second conductivity type are opposite. When the first conductivity type is N type, the second conductivity type is P type. Alternatively, when the first conductivity type is P type, the second conductivity type is N type. By employing the proposed present invention, the floating base silicon controlled rectifier acts as a forward diode, and an input capacitance can be greatly reduced.
-
-
-
-
-
-
-
-
-
搜索结果
12 条记录 (耗时 0.012 秒)