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    WAFER SCALE THERMOELECTRIC ENERGY HARVESTER HAVING INTERLEAVED, OPPOSING THERMOELECTRIC LEGS AND MANUFACTURING TECHNIQUES THEREFOR
    3.
    发明申请
    WAFER SCALE THERMOELECTRIC ENERGY HARVESTER HAVING INTERLEAVED, OPPOSING THERMOELECTRIC LEGS AND MANUFACTURING TECHNIQUES THEREFOR 审中-公开
    具有互相隔离，对抗热电偶及其制造技术的WAFER SCALE THERMOELECTRIC ENERGY HARVESTER

    公开(公告)号：US20160133816A1

    公开(公告)日：2016-05-12

    申请号：US14936450

    申请日：2015-11-09

    申请人： Analog Devices, Inc.

    发明人： Jane Cornett ,  Baoxing Chen ,  William Allan Lane ,  Patrick M. McGuinness ,  Helen Berney

    IPC分类号： H01L35/32 ,  H01L35/34

    CPC分类号： H01L35/32 ,  H01L35/34

    摘要： An integrated circuit may include a substrate and a dielectric layer formed over the substrate. A plurality of p-type thermoelectric elements and a plurality of n-type thermoelectric elements may be disposed within the dielectric layer that are connected in series while alternating between the p-type and the n-type thermoelectric elements. The integrated circuit may include first and second substrates each having formed thereon a plurality of thermoelectric legs of a respective type of thermoelectric material. The first and second thermoelectric substrates also may have respective conductors, each coupled to a base of an associated thermoelectric leg and forming a mounting pad for coupling to a thermoelectric leg of the counterpart substrate. In other embodiments, one or more substrates may have trenches formed therein to capture eutectic material that facilitates bonds between components from each of the substrates and prevent inadvertent short circuits that may occur between components of the circuit system.

    摘要翻译： 集成电路可以包括在衬底上形成的衬底和介电层。 多个p型热电元件和多个n型热电元件可以设置在电介质层内，其串联连接，同时在p型和n型热电元件之间交替。 集成电路可以包括第一和第二基板，每个基板上形成有各自类型的热电材料的多个热电支脚。 第一和第二热电基片还可以具有相应的导体，每个导体耦合到相关联的热电腿的基部并且形成用于耦合到对方基板的热电支脚的安装垫。 在其它实施例中，一个或多个基板可以在其中形成沟槽，以捕获促进来自每个基板的部件之间的接合的共晶材料，并且防止可能在电路系统的部件之间发生的无意的短路。

    Wafer scale thermoelectric energy harvester having trenches for capture of eutectic material
    5.
    发明授权
    Wafer scale thermoelectric energy harvester having trenches for capture of eutectic material 有权

    公开(公告)号：US09960336B2

    公开(公告)日：2018-05-01

    申请号：US14936510

    申请日：2015-11-09

    申请人： Analog Devices, Inc.

    发明人： Jane Cornett ,  Baoxing Chen ,  William Allan Lane ,  Patrick M. McGuinness ,  Helen Berney

    IPC分类号： H01L35/04 ,  H01L35/32 ,  H01L35/34

    CPC分类号： H01L35/32 ,  H01L35/34

    摘要： An integrated circuit may include a substrate and a dielectric layer formed over the substrate. A plurality of p-type thermoelectric elements and a plurality of n-type thermoelectric elements may be disposed within the dielectric layer that are connected in series while alternating between the p-type and the n-type thermoelectric elements. The integrated circuit may include first and second substrates each having formed thereon a plurality of thermoelectric legs of a respective type of thermoelectric material. The first and second thermoelectric substrates also may have respective conductors, each coupled to a base of an associated thermoelectric leg and forming a mounting pad for coupling to a thermoelectric leg of the counterpart substrate. In other embodiments, one or more substrates may have trenches formed therein to capture eutectic material that facilitates bonds between components from each of the substrates and prevent inadvertent short circuits that may occur between components of the circuit system.

    Wafer scale thermoelectric energy harvester
    6.
    发明授权
    Wafer scale thermoelectric energy harvester 有权

    公开(公告)号：US09620698B2

    公开(公告)日：2017-04-11

    申请号：US14066129

    申请日：2013-10-29

    申请人： Analog Devices, Inc.

    发明人： William Allan Lane ,  Baoxing Chen

    IPC分类号： H01L35/04 ,  H01L35/32 ,  H01L27/16

    CPC分类号： H01L35/32 ,  H01L27/16

    摘要： An integrated circuit may include a substrate and a dielectric layer formed over the substrate. A plurality of p-type thermoelectric elements and a plurality of n-type thermoelectric elements may be disposed within the dielectric layer. The p-type thermoelectric elements and the n-type thermoelectric elements may be connected in series while alternating between the p-type and the n-type thermoelectric elements.

    WAFER SCALE THERMOELECTRIC ENERGY HARVESTER HAVING TRENCHES FOR CAPTURE OF EUTECTIC MATERIAL
    7.
    发明申请
    WAFER SCALE THERMOELECTRIC ENERGY HARVESTER HAVING TRENCHES FOR CAPTURE OF EUTECTIC MATERIAL 有权
    具有用于捕获保护材料的波纹管的热定型热电收割机

    公开(公告)号：US20160064637A1

    公开(公告)日：2016-03-03

    申请号：US14936510

    申请日：2015-11-09

    申请人： Analog Devices, Inc.

    发明人： Jane Cornett ,  Baoxing Chen ,  William Allan Lane ,  Patrick M. McGuinness ,  Helen Berney

    IPC分类号： H01L35/32 ,  H01L35/34

    CPC分类号： H01L35/32 ,  H01L35/34

    摘要： An integrated circuit may include a substrate and a dielectric layer formed over the substrate. A plurality of p-type thermoelectric elements and a plurality of n-type thermoelectric elements may be disposed within the dielectric layer that are connected in series while alternating between the p-type and the n-type thermoelectric elements. The integrated circuit may include first and second substrates each having formed thereon a plurality of thermoelectric legs of a respective type of thermoelectric material. The first and second thermoelectric substrates also may have respective conductors, each coupled to a base of an associated thermoelectric leg and forming a mounting pad for coupling to a thermoelectric leg of the counterpart substrate. In other embodiments, one or more substrates may have trenches formed therein to capture eutectic material that facilitates bonds between components from each of the substrates and prevent inadvertent short circuits that may occur between components of the circuit system.

    摘要翻译： 集成电路可以包括在衬底上形成的衬底和介电层。 多个p型热电元件和多个n型热电元件可以设置在电介质层内，其串联连接，同时在p型和n型热电元件之间交替。 集成电路可以包括第一和第二基板，每个基板上形成有各自类型的热电材料的多个热电支脚。 第一和第二热电基片还可以具有相应的导体，每个导体耦合到相关联的热电腿的基部并且形成用于耦合到对方基板的热电支脚的安装垫。 在其它实施例中，一个或多个基板可以在其中形成沟槽，以捕获促进来自每个基板的部件之间的接合的共晶材料，并且防止可能在电路系统的部件之间发生的无意的短路。

    Wafer scale thermoelectric energy harvester having interleaved, opposing thermoelectric legs and manufacturing techniques therefor
    8.
    发明授权
    Wafer scale thermoelectric energy harvester having interleaved, opposing thermoelectric legs and manufacturing techniques therefor 有权

    公开(公告)号：US10224474B2

    公开(公告)日：2019-03-05

    申请号：US14936450

    申请日：2015-11-09

    申请人： Analog Devices, Inc.

    发明人： Jane Cornett ,  Baoxing Chen ,  William Allan Lane ,  Patrick M. McGuinness ,  Helen Berney

    IPC分类号： H01L35/32 ,  H01L35/34

    摘要： An integrated circuit may include a substrate and a dielectric layer formed over the substrate. A plurality of p-type thermoelectric elements and a plurality of n-type thermoelectric elements may be disposed within the dielectric layer that are connected in series while alternating between the p-type and the n-type thermoelectric elements. The integrated circuit may include first and second substrates each having formed thereon a plurality of thermoelectric legs of a respective type of thermoelectric material. The first and second thermoelectric substrates also may have respective conductors, each coupled to a base of an associated thermoelectric leg and forming a mounting pad for coupling to a thermoelectric leg of the counterpart substrate. In other embodiments, one or more substrates may have trenches formed therein to capture eutectic material that facilitates bonds between components from each of the substrates and prevent inadvertent short circuits that may occur between components of the circuit system.