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    Method for depositing and curing low-k films for gapfill and conformal film applications
    5.
    发明授权
    Method for depositing and curing low-k films for gapfill and conformal film applications 有权
    沉积和固化低k膜以进行间隙填充和保形膜应用的方法

    公开(公告)号：US07790634B2

    公开(公告)日：2010-09-07

    申请号：US11753918

    申请日：2007-05-25

    申请人： Jeffrey C. Munro ,  Srinivas D. Nemani

    发明人： Jeffrey C. Munro ,  Srinivas D. Nemani

    IPC分类号： H01L21/31 ,  H01L21/469

    CPC分类号： H01L21/31633 ,  C23C16/401 ,  C23C16/452 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/3105

    摘要： Methods of making a silicon oxide layer on a substrate are described. The methods may include forming the silicon oxide layer on the substrate in a reaction chamber by reacting an atomic oxygen precursor and a silicon precursor and depositing reaction products on the substrate. The atomic oxygen precursor is generated outside the reaction chamber. The methods also include heating the silicon oxide layer at a temperature of about 600° C. or less, and exposing the silicon oxide layer to an induced coupled plasma. Additional methods are described where the deposited silicon oxide layer is cured by exposing the layer to ultra-violet light, and also exposing the layer to an induced coupled plasma.

    摘要翻译： 描述了在衬底上制造氧化硅层的方法。 所述方法可以包括通过使原子氧前体和硅前体反应并在基底上沉积反应产物，在反应室中的衬底上形成氧化硅层。 原子氧前体在反应室外产生。 所述方法还包括在约600℃或更低的温度下加热氧化硅层，并将氧化硅层暴露于感应耦合等离子体。 描述了通过将层暴露于紫外光而使沉积的氧化硅层固化并且还将该层暴露于感应耦合等离子体的附加方法。

    POST DEPOSITION PLASMA TREATMENT TO INCREASE TENSILE STRESS OF HDP-CVD SIO2
    6.
    发明申请
    POST DEPOSITION PLASMA TREATMENT TO INCREASE TENSILE STRESS OF HDP-CVD SIO2 失效
    后沉积等离子体处理以提高HDP-CVD SIO2的拉伸应力

    公开(公告)号：US20090035918A1

    公开(公告)日：2009-02-05

    申请号：US12252260

    申请日：2008-10-15

    申请人： Xiaolin Chen ,  Srinivas D. Nemani ,  DongQing Li ,  Jeffrey C. Munro ,  Marlon E. Menezes

    发明人： Xiaolin Chen ,  Srinivas D. Nemani ,  DongQing Li ,  Jeffrey C. Munro ,  Marlon E. Menezes

    IPC分类号： H01L21/76

    CPC分类号： H01L21/3105 ,  C23C16/402 ,  C23C16/56 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/31612

    摘要： Methods of forming a dielectric layer where the tensile stress of the layer is increased by a plasma treatment at an elevated position are described. In one embodiment, oxide and nitride layers are deposited on a substrate and patterned to form an opening. A trench is etched into the substrate. The substrate is transferred into a chamber suitable for dielectric deposition. A dielectric layer is deposited over the substrate, filling the trench and covering mesa regions adjacent to the trench. The substrate is raised to an elevated position above the substrate support and exposed to a plasma which increases the tensile stress of the substrate. The substrate is removed from the dielectric deposition chamber, and portions of the dielectric layer are removed so that the dielectric layer is even with the topmost portion of the nitride layer. The nitride and pad oxide layers are removed to form the STI structure.

    摘要翻译： 描述了通过在升高的位置处的等离子体处理来增加层的拉伸应力的电介质层的形成方法。 在一个实施例中，将氧化物和氮化物层沉积在衬底上并图案化以形成开口。 沟槽被蚀刻到衬底中。 将基底转移到适合于电介质沉积的室中。 介电层沉积在衬底上，填充沟槽并覆盖与沟槽相邻的台面区域。 将衬底升高到衬底支撑件上方的升高位置并暴露于等离子体，这增加了衬底的拉伸应力。 从电介质沉积室取出基板，除去介质层的部分，使得介质层与氮化物层的最上部分均匀。 去除氮化物层和衬垫氧化物层以形成STI结构。

    Post deposition plasma treatment to increase tensile stress of HDP-CVD SIO2
    7.
    发明授权
    Post deposition plasma treatment to increase tensile stress of HDP-CVD SIO2 失效
    后沉积等离子体处理以增加HDP-CVD SIO2的拉伸应力

    公开(公告)号：US07745351B2

    公开(公告)日：2010-06-29

    申请号：US12252260

    申请日：2008-10-15

    申请人： Xiaolin Chen ,  Srinivas D. Nemani ,  DongQing Li ,  Jeffrey C. Munro ,  Marlon E. Menezes

    发明人： Xiaolin Chen ,  Srinivas D. Nemani ,  DongQing Li ,  Jeffrey C. Munro ,  Marlon E. Menezes

    IPC分类号： H01L21/31 ,  H01L21/469

    CPC分类号： H01L21/3105 ,  C23C16/402 ,  C23C16/56 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/31612

    摘要： Methods of forming a dielectric layer where the tensile stress of the layer is increased by a plasma treatment at an elevated position are described. In one embodiment, oxide and nitride layers are deposited on a substrate and patterned to form an opening. A trench is etched into the substrate. The substrate is transferred into a chamber suitable for dielectric deposition. A dielectric layer is deposited over the substrate, filling the trench and covering mesa regions adjacent to the trench. The substrate is raised to an elevated position above the substrate support and exposed to a plasma which increases the tensile stress of the substrate. The substrate is removed from the dielectric deposition chamber, and portions of the dielectric layer are removed so that the dielectric layer is even with the topmost portion of the nitride layer. The nitride and pad oxide layers are removed to form the STI structure.

    摘要翻译： 描述了通过在升高的位置处的等离子体处理来增加层的拉伸应力的电介质层的形成方法。 在一个实施例中，将氧化物和氮化物层沉积在衬底上并图案化以形成开口。 沟槽被蚀刻到衬底中。 将基底转移到适合于电介质沉积的室中。 介电层沉积在衬底上，填充沟槽并覆盖与沟槽相邻的台面区域。 将衬底升高到衬底支撑件上方的升高位置并暴露于等离子体，这增加了衬底的拉伸应力。 从电介质沉积室取出基板，除去介质层的部分，使得介质层与氮化物层的最上部分均匀。 去除氮化物层和衬垫氧化物层以形成STI结构。

    Dopant activation in doped semiconductor substrates
    8.
    发明授权
    Dopant activation in doped semiconductor substrates 失效
    掺杂半导体衬底中的掺杂剂活化

    公开(公告)号：US07989366B2

    公开(公告)日：2011-08-02

    申请号：US11844810

    申请日：2007-08-24

    申请人： Jeffrey C. Munro ,  Srinivas D. Nemani ,  Young S. Lee ,  Marlon Menezes ,  Christopher Dennis Bencher ,  Vijay Parihar

    发明人： Jeffrey C. Munro ,  Srinivas D. Nemani ,  Young S. Lee ,  Marlon Menezes ,  Christopher Dennis Bencher ,  Vijay Parihar

    IPC分类号： H01L21/00

    CPC分类号： H01L21/268 ,  H01L21/26513

    摘要： Methods are disclosed for activating dopants in a doped semiconductor substrate. A carbon precursor is flowed into a substrate processing chamber within which the doped semiconductor substrate is disposed. A plasma is formed from the carbon precursor in the substrate processing chamber. A carbon film is deposited over the substrate with the plasma. A temperature of the substrate is maintained while depositing the carbon film less than 500° C. The deposited carbon film is exposed to electromagnetic radiation for a period less than 10 ms, and has an extinction coefficient greater than 0.3 at a wavelength comprised by the electromagnetic radiation.

    摘要翻译： 公开了用于激活掺杂半导体衬底中的掺杂剂的方法。 碳前体流入其中设置掺杂半导体衬底的衬底处理室。 在基板处理室中由碳前体形成等离子体。 用等离子体沉积在衬底上的碳膜。 在沉积低于500℃的碳膜的同时保持基板的温度。沉积的碳膜暴露于电磁辐射小于10ms的时间段，并且在电磁波包括的波长处具有大于0.3的消光系数 辐射。

    Post deposition plasma treatment to increase tensile stress of HDP-CVD SIO2
    9.
    发明授权
    Post deposition plasma treatment to increase tensile stress of HDP-CVD SIO2 失效
    后沉积等离子体处理以增加HDP-CVD SIO2的拉伸应力

    公开(公告)号：US07465680B2

    公开(公告)日：2008-12-16

    申请号：US11221303

    申请日：2005-09-07

    申请人： Xiaolin Chen ,  Srinivas D. Nemani ,  DongQing Li ,  Jeffrey C. Munro ,  Marlon E. Menezes

    发明人： Xiaolin Chen ,  Srinivas D. Nemani ,  DongQing Li ,  Jeffrey C. Munro ,  Marlon E. Menezes

    IPC分类号： H01L21/31 ,  H01L21/469

    CPC分类号： H01L21/3105 ,  C23C16/402 ,  C23C16/56 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/31612

    摘要： A plasma treatment process for increasing the tensile stress of a silicon wafer is described. Following deposition of a dielectric layer on a substrate, the substrate is lifted to an elevated position above the substrate receiving surface and exposed to a plasma treatment process which treats both the top and bottom surface of the wafer and increases the tensile stress of the deposited layer. Another embodiment of the invention involves biasing of the substrate prior to plasma treatment to bombard the wafer with plasma ions and raise the temperature of the substrate. In another embodiment of the invention, a two-step plasma treatment process can be used where the substrate is first exposed to a plasma at a processing position directly after deposition, and then raised to an elevated position where both the top and bottom of the wafer are exposed to the plasma.

    摘要翻译： 描述了用于增加硅晶片的拉伸应力的等离子体处理工艺。 在基底上沉积介电层之后，将衬底提升到衬底接收表面上方的升高位置并暴露于等离子体处理工艺，其处理晶片的顶表面和底表面并增加沉积层的拉伸应力 。 本发明的另一实施例涉及在等离子体处理之前偏压衬底以用等离子体离子轰击晶片并提高衬底的温度。 在本发明的另一个实施例中，可以使用两步等离子体处理工艺，其中首先在沉积后直接在处理位置处暴露于等离子体，然后升高到晶片的顶部和底部两者的升高位置 暴露于等离子体。