利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

10 条记录 (耗时 0.023 秒)

    Rapid thermal annealing of doped polycrystalline silicon structures formed in a single-wafer cluster tool
    1.
    发明授权
    Rapid thermal annealing of doped polycrystalline silicon structures formed in a single-wafer cluster tool 有权
    在单晶片集成工具中形成的掺杂多晶硅结构的快速热退火

    公开(公告)号：US06204198B1

    公开(公告)日：2001-03-20

    申请号：US09447174

    申请日：1999-11-22

    申请人： Aditi D. Banerjee ,  Douglas E. Mercer ,  Rick L. Wise

    发明人： Aditi D. Banerjee ,  Douglas E. Mercer ,  Rick L. Wise

    IPC分类号： H01L2131

    CPC分类号： H01L21/28035

    摘要： An embodiment of the instant invention is a method of fabricating an electronic device over a semiconductor substrate, the method comprising the steps of: forming a doped polycrystalline silicon layer insulatively disposed over the semiconductor substrate; and subjecting the doped polycrystalline silicon layer to a temperature of around 700 to 1100 C. in an oxidizing ambient for a period of around 5 to 120 seconds. Preferably, the oxidizing ambient is comprised of: O2,O3, NO, N2O, H2O, and any combination thereof. The temperature is, preferably, around 950 to 1050 C. (more preferably around 1000 C.). The step of subjecting the doped polycrystalline silicon layer to a temperature of around 700 to 1100 C. in an oxidizing ambient for a period of around 5 to 120 seconds, preferably, forms an oxide layer on the polycrystalline silicon layer, which has a thickness which is, preferably, greater than the thickness of a native oxide layer. More preferably, it has a thickness which is greater than 3 nm (more preferably greater than 2 nm). In an alternative embodiment, the thickness of the oxide layer is less than 20 nm (more preferably, less than 10 nm thick).

    摘要翻译： 本发明的一个实施例是一种在半导体衬底上制造电子器件的方法，该方法包括以下步骤：形成绝缘地设置在半导体衬底上的掺杂多晶硅层; 并在氧化环境中将掺杂的多晶硅层经受约700至1100℃的温度约5至120秒的时间。 优选地，氧化环境包括：O 2，O 3，NO，N 2 O，H 2 O及其任何组合。 温度优选为950〜1050℃左右（更优选为1000℃左右）。 在氧化环境中将掺杂多晶硅层的温度约为700〜1100℃的温度进行约5〜120秒的时间，优选在多晶硅层上形成氧化物层，其厚度为 优选地大于天然氧化物层的厚度。 更优选地，其厚度大于3nm（更优选大于2nm）。 在替代实施例中，氧化物层的厚度小于20nm（更优选小于10nm厚）。

    Memory cell with transistors having relatively high threshold voltages in response to selective gate doping
    3.
    发明授权
    Memory cell with transistors having relatively high threshold voltages in response to selective gate doping 有权
    具有响应于选择性栅极掺杂的具有相对高的阈值电压的晶体管的存储单元

    公开(公告)号：US06773972B2

    公开(公告)日：2004-08-10

    申请号：US10023113

    申请日：2001-12-13

    申请人： Andrew Marshall ,  Youngmin Kim ,  David B Scott ,  Douglas E. Mercer

    发明人： Andrew Marshall ,  Youngmin Kim ,  David B Scott ,  Douglas E. Mercer

    IPC分类号： H01L21338

    CPC分类号： G11C11/412 ,  H01L27/1104

    摘要： A method of forming a semiconductor circuit (20). The method forms a first transistor (NT1) using various steps, such as by forming a first source/drain region (361) as a first doped region in a fixed relationship to a semiconductor substrate (22) and forming a second source/drain region (362) as a second doped region in a fixed relationship to the semiconductor substrate. The second doped region and the first doped region are of a same conductivity type. Additionally, the first transistor is formed by forming a first gate (283) in a fixed relationship to the first source/drain region and the second drain region. The method also forms a second transistor (ST1) using various steps, such as by forming a third source/drain region (341) as a third doped region in a fixed relationship to the semiconductor substrate and forming a fourth source/drain region (342) as a fourth doped region in a fixed relationship to the semiconductor substrate. The fourth doped region and the third doped region are of the same conductivity type as the first and second doped regions. Additionally, the second transistor is formed by forming a second gate (282) in a fixed relationship to the third source/drain region and the fourth drain region. Also in the preferred embodiment method, the steps of forming the first gate and the second gate comprising forming the first gate to comprise a first dopant concentration and forming the second gate to comprise a second dopant concentration different from the first dopant concentration.

    摘要翻译： 一种形成半导体电路（20）的方法。 该方法使用各种步骤形成第一晶体管（NT1），例如通过以与半导体衬底（22）固定的关系形成第一源/漏区（361）作为第一掺杂区，并形成第二源/漏区 （362）作为与半导体衬底固定关系的第二掺杂区域。 第二掺杂区域和第一掺杂区域具有相同的导电类型。 另外，第一晶体管通过以与第一源极/漏极区域和第二漏极区域固定的关系形成第一栅极（283）而形成。 该方法还使用各种步骤形成第二晶体管（ST1），例如通过以与半导体衬底固定的关系形成作为第三掺杂区域的第三源极/漏极区域（341）并形成第四源极/漏极区域（342） ）作为与半导体衬底固定关系的第四掺杂区域。 第四掺杂区域和第三掺杂区域具有与第一和第二掺杂区域相同的导电类型。 另外，通过以与第三源极/漏极区域和第四漏极区域固定的关系形成第二栅极（282）来形成第二晶体管。 同样在优选实施方案中，形成第一栅极和第二栅极的步骤包括形成第一栅极以包括第一掺杂剂浓度并形成第二栅极以包括不同于第一掺杂剂浓度的第二掺杂剂浓度。

    Metal-halogen physical vapor deposition for semiconductor device defect reduction
    9.
    发明授权
    Metal-halogen physical vapor deposition for semiconductor device defect reduction 有权
    用于半导体器件缺陷的金属卤素物理气相沉积

    公开(公告)号：US07208398B2

    公开(公告)日：2007-04-24

    申请号：US10903805

    申请日：2004-07-30

    申请人： Peijun J. Chen ,  Duofeng Yue ,  Douglas E. Mercer ,  Noel Russell

    发明人： Peijun J. Chen ,  Duofeng Yue ,  Douglas E. Mercer ,  Noel Russell

    IPC分类号： H01L21/28

    CPC分类号： H01L21/28518 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/665 ,  H01L29/78

    摘要： The present invention provides a method of manufacturing a metal silicide electrode (100) for a semiconductor device (110). The method comprises depositing by physical vapor deposition, halogen atoms (120) and transition metal atoms (130) to form a halogen-containing metal layer (140) on a semiconductor substrate (150). The halogen-containing metal layer and the semiconductor substrate are reacted to form a metal silicide electrode. Other aspects of the present invention include a method of manufacturing an integrated circuit (400) comprising the metal silicide electrode.

    摘要翻译： 本发明提供一种制造用于半导体器件（110）的金属硅化物电极（100）的方法。 该方法包括通过物理气相沉积沉积卤素原子（120）和过渡金属原子（130）以在半导体衬底（150）上形成含卤素的金属层（140）。 使含卤素金属层和半导体基板反应形成金属硅化物电极。 本发明的其它方面包括制造包括金属硅化物电极的集成电路（400）的方法。