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    Memory cell with transistors having relatively high threshold voltages in response to selective gate doping
    1.
    发明授权
    Memory cell with transistors having relatively high threshold voltages in response to selective gate doping 有权
    具有响应于选择性栅极掺杂的具有相对高的阈值电压的晶体管的存储单元

    公开(公告)号：US06773972B2

    公开(公告)日：2004-08-10

    申请号：US10023113

    申请日：2001-12-13

    申请人： Andrew Marshall ,  Youngmin Kim ,  David B Scott ,  Douglas E. Mercer

    发明人： Andrew Marshall ,  Youngmin Kim ,  David B Scott ,  Douglas E. Mercer

    IPC分类号： H01L21338

    CPC分类号： G11C11/412 ,  H01L27/1104

    摘要： A method of forming a semiconductor circuit (20). The method forms a first transistor (NT1) using various steps, such as by forming a first source/drain region (361) as a first doped region in a fixed relationship to a semiconductor substrate (22) and forming a second source/drain region (362) as a second doped region in a fixed relationship to the semiconductor substrate. The second doped region and the first doped region are of a same conductivity type. Additionally, the first transistor is formed by forming a first gate (283) in a fixed relationship to the first source/drain region and the second drain region. The method also forms a second transistor (ST1) using various steps, such as by forming a third source/drain region (341) as a third doped region in a fixed relationship to the semiconductor substrate and forming a fourth source/drain region (342) as a fourth doped region in a fixed relationship to the semiconductor substrate. The fourth doped region and the third doped region are of the same conductivity type as the first and second doped regions. Additionally, the second transistor is formed by forming a second gate (282) in a fixed relationship to the third source/drain region and the fourth drain region. Also in the preferred embodiment method, the steps of forming the first gate and the second gate comprising forming the first gate to comprise a first dopant concentration and forming the second gate to comprise a second dopant concentration different from the first dopant concentration.

    摘要翻译： 一种形成半导体电路（20）的方法。 该方法使用各种步骤形成第一晶体管（NT1），例如通过以与半导体衬底（22）固定的关系形成第一源/漏区（361）作为第一掺杂区，并形成第二源/漏区 （362）作为与半导体衬底固定关系的第二掺杂区域。 第二掺杂区域和第一掺杂区域具有相同的导电类型。 另外，第一晶体管通过以与第一源极/漏极区域和第二漏极区域固定的关系形成第一栅极（283）而形成。 该方法还使用各种步骤形成第二晶体管（ST1），例如通过以与半导体衬底固定的关系形成作为第三掺杂区域的第三源极/漏极区域（341）并形成第四源极/漏极区域（342） ）作为与半导体衬底固定关系的第四掺杂区域。 第四掺杂区域和第三掺杂区域具有与第一和第二掺杂区域相同的导电类型。 另外，通过以与第三源极/漏极区域和第四漏极区域固定的关系形成第二栅极（282）来形成第二晶体管。 同样在优选实施方案中，形成第一栅极和第二栅极的步骤包括形成第一栅极以包括第一掺杂剂浓度并形成第二栅极以包括不同于第一掺杂剂浓度的第二掺杂剂浓度。

    Multifunctional doped conducting polymer-based field effect devices
    7.
    发明申请
    Multifunctional doped conducting polymer-based field effect devices 审中-公开
    多功能掺杂导电聚合物基场效应器件

    公开(公告)号：US20060240324A1

    公开(公告)日：2006-10-26

    申请号：US11089676

    申请日：2005-03-25

    申请人： Arthur Epstein ,  Oliver Waldmann ,  June Hyoung Park ,  Nan-Rong Chiou ,  Youngmin Kim

    发明人： Arthur Epstein ,  Oliver Waldmann ,  June Hyoung Park ,  Nan-Rong Chiou ,  Youngmin Kim

    IPC分类号： H01M4/60 ,  H01M4/58 ,  H01L27/12

    CPC分类号： H01L51/052 ,  H01L51/0034 ,  H01L51/0035 ,  H01L51/0037 ,  H01L51/0545 ,  H01L51/105

    摘要： Electric field driven devices and methods of operation are provided. Each device use one or more doped conducting polymers to provide multifunctional responses to applied electric field. The device includes an electrically conductive layer operative to provide a gate contact for the device; a conducting polymer layer operative to provide source and drain contacts for the device, and an active layer; and an insulating polymer layer formed between the electrically conductive layer and the conducting polymer layer, wherein the layers in combination allow the device to be operative to perform at least two of a plurality of response functions.

    摘要翻译： 提供电场驱动装置和操作方法。 每个器件使用一种或多种掺杂的导电聚合物来提供对施加的电场的多功能响应。 该装置包括可操作地为装置提供栅极接触的导电层; 可操作地提供用于所述装置的源极和漏极触点的导电聚合物层和有源层; 以及形成在所述导电层和所述导电聚合物层之间的绝缘聚合物层，其中所述层组合允许所述装置可操作以执行多个响应函数中的至少两个。

    Tunable sidewall spacer process for CMOS integrated circuits
    8.
    发明申请
    Tunable sidewall spacer process for CMOS integrated circuits 审中-公开
    CMOS集成电路的可调谐侧壁间隔工艺

    公开(公告)号：US20050164443A1

    公开(公告)日：2005-07-28

    申请号：US11084473

    申请日：2005-03-18

    申请人： Youngmin Kim ,  Shawn Walsh

    发明人： Youngmin Kim ,  Shawn Walsh

    IPC分类号： H01L21/8238 ,  H01L21/301 ,  H01L21/46 ,  H01L21/78

    CPC分类号： H01L21/823864 ,  H01L21/823814

    摘要： A mixed voltage CMOS process for high reliability and high performance core transistors and input-output transistors with reduced mask steps. A gate stack (30) is formed over the silicon substrate (10). Ion implantation is performed of a first species and a second species to produce the doping profiles (70, 80, 90, 100) in the input-output transistors.

    摘要翻译： 用于高可靠性和高性能核心晶体管和输入输出晶体管的混合电压CMOS工艺，减少了掩模步骤。 在硅衬底（10）上形成栅叠层（30）。 对第一种和第二种进行离子注入，以在输入输出晶体管中产生掺杂分布（70,80,90,100）。

    Transistors having selectively doped channel regions
    9.
    发明授权
    Transistors having selectively doped channel regions 有权
    具有选择性掺杂沟道区的晶体管

    公开(公告)号：US06730555B2

    公开(公告)日：2004-05-04

    申请号：US10153033

    申请日：2002-05-22

    申请人： Youngmin Kim ,  Amitava Chatterjee

    发明人： Youngmin Kim ,  Amitava Chatterjee

    IPC分类号： H01L218238

    CPC分类号： H01L21/823842

    摘要： An integrated semiconductor system is provided that is formed on a substrate 10. A dual implant mask 26 is used to change the characteristics of semiconductor devices formed in regions of the substrate 10 having different characteristics. Transistors 50 and 52 can be formed on the same substrate 10 and have different electrical characteristics.

    摘要翻译： 提供了形成在基板10上的集成半导体系统。双注入掩模26用于改变在具有不同特性的基板10的区域中形成的半导体器件的特性。 晶体管50和52可以形成在相同的基板10上并且具有不同的电特性。