Abstract:
An integrated circuit device includes a memory controller coupleable to a memory. The memory controller to schedule memory accesses to regions of the memory based on memory timing parameters specific to the regions. A method includes receiving a memory access request at a memory device. The method further includes accessing, from a timing data store of the memory device, data representing a memory timing parameter specific to a region of the memory cell circuitry targeted by the memory access request. The method also includes scheduling, at the memory controller, the memory access request based on the data.
Abstract:
A method and apparatus for rendering graphics is disclosed. An edge list and polygon list are generated from a polygon based model. Each polygon is handled in parallel. For each polygon, an active edge pair table is generated based on the polygon list and edge list. Active edge pairs are selected from the active edge table based on a minimum position on a predetermined axis. All active edge pairs that intersect a scan line are processed. The processing includes computing a color value for each pixel lying between points where each active edge pair intersects the scan line. The pixel is then rendered and the active edge table is updated.
Abstract:
A method, a system and a computer-readable medium for writing to a cache memory are provided. The method comprises maintaining a write count associated with a set, the set containing a memory block associated with a physical block address. A mapping from a logical address to the physical address of the block is also maintained. The method shifts the mapping based on the value of the write count and writes data to the block based on the mapping.
Abstract:
An integrated circuit device includes a memory controller coupleable to a memory. The memory controller to schedule memory accesses to regions of the memory based on memory timing parameters specific to the regions. A method includes receiving a memory access request at a memory device. The method further includes accessing, from a timing data store of the memory device, data representing a memory timing parameter specific to a region of the memory cell circuitry targeted by the memory access request. The method also includes scheduling, at the memory controller, the memory access request based on the data.