公开(公告)号：US20220020605A1

公开(公告)日：2022-01-20

申请号：US16933813

申请日：2020-07-20

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Kay Stefan ESSIG ,  Jean Marc YANNOU ,  Bradford FACTOR

IPC: H01L21/56 ,  H01L23/492 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L23/498

Abstract: A semiconductor package structure and a method of manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a conductive base, a first semiconductor die, a first conductive pillar, and a first encapsulant. The conductive base has a first surface. The first semiconductor die is disposed on the first surface of the conductive base. The first conductive pillar is disposed on the first semiconductor die. The first encapsulant is disposed on the first surface of the conductive base. The first encapsulant encapsulates the first semiconductor die. The first encapsulant includes an opening defined by the first conductive pillar.

公开(公告)号：US20170294389A1

公开(公告)日：2017-10-12

申请号：US15482464

申请日：2017-04-07

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Bradford FACTOR ,  Rich RICE ,  Mark GERBER

IPC: H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L23/373 ,  H01L25/065

CPC classification number: H01L23/562 ,  H01L23/3735 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00

Abstract: A semiconductor package structure includes a substrate, a first semiconductor device, a first encapsulant and a second encapsulant. The substrate has a first coefficient of thermal expansion CTE1. The first semiconductor device is disposed adjacent to a first surface of the substrate. The first encapsulant is disposed on the first surface of the substrate, and covers at least a portion of the first semiconductor device. The first encapsulant has a second coefficient of thermal expansion CTE2. The second encapsulant is disposed on a second surface of the substrate and has a third coefficient of thermal expansion CTE3. A difference between CTE1 and CTE2 is substantially equal to a difference between CTE1 and CTE3.