公开(公告)号：US20190148280A1

公开(公告)日：2019-05-16

申请号：US16247441

申请日：2019-01-14

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Chun-Che Lee ,  Ming-Chiang Lee ,  Yuan-Chang Su ,  Tien-Szu Chen ,  Chih-Cheng Lee ,  You-Lung Yen

IPC: H01L23/498 ,  H01L21/48 ,  H05K1/11 ,  H05K3/00

Abstract: A semiconductor substrate and a manufacturing method thereof are provided. The semiconductor substrate includes a dielectric layer, a circuit layer, a first protection layer and a plurality of conductive posts. The dielectric layer has a first surface and a second surface that are opposite to each other. The circuit layer is embedded in the dielectric layer and is exposed from the first surface. The first protection layer covers a portion of the first circuit layer and defines a plurality of holes that expose a remaining portion of the first circuit layer. The conductive posts are formed in the holes.

公开(公告)号：US20190109117A1

公开(公告)日：2019-04-11

申请号：US16152270

申请日：2018-10-04

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Hsu-Nan Fang ,  Chun-Jun Zhuang ,  Yung I. Yeh ,  Ming-Chiang Lee

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor device package includes a first redistribution layer (RDL), a first die, a second die, a second RDL and an encapsulant. The first die is disposed on the first RDL and is electrically connected to the first RDL. The first die has a first electrical contact. The second die is disposed on the first RDL and is electrically connected to the first RDL. The second die has a first electrical contact. The second RDL is surrounded by the first RDL. The second RDL has a first electrical contact electrically connected to the first electrical contact of the first die and a second electrical contact electrically connected to the first electrical contact of the second die. A size of the first electrical contact of the second RDL is greater than a size of the second electrical contact of the second RDL.

公开(公告)号：US09190367B1

公开(公告)日：2015-11-17

申请号：US14520914

申请日：2014-10-22

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Kuo Hsien Liao ,  Ming-Chiang Lee ,  Cheng-Nan Lin

IPC: H01L23/02 ,  H01L23/00

CPC classification number: H01L23/3121 ,  H01L21/561 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/552 ,  H01L24/01 ,  H01L24/97 ,  H01L25/16 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2225/1041 ,  H01L2924/15311 ,  H01L2924/19106 ,  H01L2924/3025 ,  H01L2224/85 ,  H01L2224/81

Abstract: The semiconductor package includes a substrate, a plurality of components, an interposer, an electrical interconnect and a first package body. The substrate has a first surface and a second surface opposite to the first surface. A first component is mounted on the first surface of the substrate, and a second component is mounted on the second surface of the substrate. The interposer has a first surface. The electrical interconnect connects the first surface of the interposer to the second surface of the substrate. The first package body is disposed on the second surface of the substrate and encapsulates the second component, the electrical interconnect and at least a portion of the interposer.

Abstract translation: 半导体封装包括衬底，多个部件，插入器，电互连和第一封装体。 基板具有与第一表面相对的第一表面和第二表面。 第一部件安装在基板的第一表面上，第二部件安装在基板的第二表面上。 插入器具有第一表面。 电互连将插入件的第一表面连接到基板的第二表面。 第一封装体设置在基板的第二表面上并且封装第二部件，电互连以及插入件的至少一部分。

公开(公告)号：US10181438B2

公开(公告)日：2019-01-15

申请号：US14523733

申请日：2014-10-24

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Chun-Che Lee ,  Ming-Chiang Lee ,  Yuan-Chang Su ,  Tien-Szu Chen ,  Chih-Cheng Lee ,  You-Lung Yen

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/498 ,  H05K1/11 ,  H05K3/00 ,  H01L21/48 ,  H05K3/46

Abstract: A semiconductor substrate and a manufacturing method thereof are provided. The semiconductor substrate includes a dielectric layer, a circuit layer, a first protection layer and a plurality of conductive posts. The dielectric layer has a first surface and a second surface that are opposite to each other. The circuit layer is embedded in the dielectric layer and is exposed from the first surface. The first protection layer covers a portion of the first circuit layer and defines a plurality of holes that expose a remaining portion of the first circuit layer. The conductive posts are formed in the holes.

公开(公告)号：US12218077B2

公开(公告)日：2025-02-04

申请号：US17705216

申请日：2022-03-25

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Nan Lin ,  Ming-Chiang Lee ,  Yung-I Yeh

IPC: H01L23/00 ,  H01L23/538 ,  H01L25/18

Abstract: A semiconductor device package is disclosed. The semiconductor device package includes a carrier, a first electronic component disposed on the carrier and a support component disposed on the carrier. The semiconductor device package also includes a second electronic component disposed on the first electronic component and supported by the support component.

公开(公告)号：US10797022B2

公开(公告)日：2020-10-06

申请号：US16152270

申请日：2018-10-04

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Hsu-Nan Fang ,  Chun-Jun Zhuang ,  Yung I. Yeh ,  Ming-Chiang Lee

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/367 ,  H01L21/48 ,  H01L23/498

Abstract: A semiconductor device package includes a first redistribution layer (RDL), a first die, a second die, a second RDL and an encapsulant. The first die is disposed on the first RDL and is electrically connected to the first RDL. The first die has a first electrical contact. The second die is disposed on the first RDL and is electrically connected to the first RDL. The second die has a first electrical contact. The second RDL is surrounded by the first RDL. The second RDL has a first electrical contact electrically connected to the first electrical contact of the first die and a second electrical contact electrically connected to the first electrical contact of the second die. A size of the first electrical contact of the second RDL is greater than a size of the second electrical contact of the second RDL.

公开(公告)号：US09578737B2

公开(公告)日：2017-02-21

申请号：US14169640

申请日：2014-01-31

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Kuo-Hua Chen ,  Ming-Chiang Lee ,  Tsung-Hsun Lee ,  Chen-Chuan Fan

IPC: H05K7/00 ,  H05K1/02 ,  H01L23/31 ,  H01L23/498 ,  H05K1/09 ,  H05K1/11

CPC classification number: H05K1/0298 ,  H01L23/3128 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K1/09 ,  H05K1/116 ,  H05K2201/09781

Abstract: A substrate structure is provided. The substrate structure includes a number of traces, a substrate core, a number of first metal tiles, a number of second metal tiles, a number of first electrically-functioning circuits, and a number of second electrically-functioning circuits. The substrate core has a first surface and a second surface opposite to the first surface. The traces, the first metal tiles, and the first electrically-functioning circuits are disposed on the first surface and add up to a first metal structure proportion, and the second metal tiles and the second electrically-functioning circuits are disposed on the second surface and add up to a second metal structure proportion. The difference between the first metal structure proportion and the second metal structure proportion is within 15%.

Abstract translation: 提供了基板结构。 衬底结构包括多个迹线，衬底芯，多个第一金属片，多个第二金属片，多个第一电功能电路和多个第二电功能电路。 衬底芯具有与第一表面相对的第一表面和第二表面。 迹线，第一金属瓦片和第一电功能电路设置在第一表面上并加到第一金属结构比例上，第二金属瓦片和第二电功能电路设置在第二表面上， 加起来第二个金属结构比例。 第一金属结构比例与第二金属结构比例之差在15％以内。