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    Video quality adaptive variable-rate buffering method and system for stabilizing a sampled video signal
    1.
    发明授权
    Video quality adaptive variable-rate buffering method and system for stabilizing a sampled video signal 有权
    用于稳定采样视频信号的视频质量自适应可变速率缓冲方法和系统

    公开(公告)号：US07471340B1

    公开(公告)日：2008-12-30

    申请号：US11088447

    申请日：2005-03-24

    申请人： Ahsan Chowdhury ,  Rahul Singh ,  John L. Melanson ,  James A. Antone

    发明人： Ahsan Chowdhury ,  Rahul Singh ,  John L. Melanson ,  James A. Antone

    IPC分类号： H03M1/12 ,  H03L7/00 ,  H04N9/64

    CPC分类号： H03L7/1974 ,  H03L7/08 ,  H03L7/0805 ,  H03L2207/50 ,  H04N5/12 ,  H04N5/213 ,  H04N5/765 ,  H04N5/85 ,  H04N7/0132 ,  H04N9/8042 ,  H04N9/896 ,  H04N21/4325 ,  H04N21/44004

    摘要： A video quality adaptive variable-rate buffering method and system for stabilizing a sampled video signal reduces the buffer size required to compensate for line-to-line variations in an unstable video source. A video signal is sampled at a predetermined rate and decimated by a selectable decimation factor prior to buffering. By selecting different decimation factors, the effective length of the buffer is changed from short duration for stable input signals and to longer duration for unstable input signals. A video signal quality detector is employed to provide a selection input that adjusts the decimation factor and also the loop bandwidth of a clock generator that provides the output clock for the buffer, which is generated from the input signal via a phase-lock loop (PLL). The operation of the system automatically varies from highly responsive for stable video input signals to less responsive for unstable video input signals, providing improved stability in the video output.

    摘要翻译： 用于稳定采样视频信号的视频质量自适应可变速率缓冲方法和系统降低了补偿不稳定视频源中的线间变化所需的缓冲器大小。 以预定的速率对视频信号进行采样，并在缓冲之前用可选择的抽取因子进行抽取。 通过选择不同的抽取因子，缓冲器的有效长度从稳定输入信号的短持续时间改变为不稳定输入信号的持续时间。 采用视频信号质量检测器来提供选择输入，其调节抽取因子以及时钟发生器的环路带宽，该时钟发生器提供缓冲器的输出时钟，该时钟发生器通过锁相环（PLL）从输入信号产生 ）。 系统的操作自动变化，从稳定的视频输入信号的高度响应到对不稳定的视频输入信号的响应不足，提高了视频输出的稳定性。

    Inverse tracking over two different clock domains
    3.
    发明申请
    Inverse tracking over two different clock domains 失效
    反向跟踪两个不同的时钟域

    公开(公告)号：US20060077296A1

    公开(公告)日：2006-04-13

    申请号：US10964556

    申请日：2004-10-13

    申请人： Daniel Gudmundson ,  John Melanson ,  Rahul Singh ,  Ahsan Chowdhury

    发明人： Daniel Gudmundson ,  John Melanson ,  Rahul Singh ,  Ahsan Chowdhury

    IPC分类号： H04N11/00

    CPC分类号： H03L7/06 ,  H03L7/0991 ,  H03L2207/50 ,  H04L7/005 ,  H04L7/0331 ,  H04N5/126

    摘要： A video decoder in which the video source clock is generated entirely in the digital domain is disclosed herein. By creating a virtual version of the source clock in a numeric oscillator, the amount of noise in the system is substantially reduced. Furthermore, by transferring the digitized video signal, sampled with an asynchronous crystal clock, into the source clock domain, the accuracy of the brightness (amplitude) and color (phase) information can be greatly enhanced.

    摘要翻译： 本文公开了视频源时钟完全在数字域中生成的视频解码器。 通过在数字振荡器中创建源时钟的虚拟版本，系统中的噪声量显着降低。 此外，通过将用异步晶体时钟采样的数字化视频信号传送到源时钟域，可以大大提高亮度（幅度）和颜色（相位）信息的精度。

    Method and apparatus for maintaining an ideal frequency ratio between numerically-controlled frequency sources
    5.
    发明授权
    Method and apparatus for maintaining an ideal frequency ratio between numerically-controlled frequency sources 有权
    用于维持数控频率源之间的理想频率比的方法和装置

    公开(公告)号：US07158045B1

    公开(公告)日：2007-01-02

    申请号：US11088446

    申请日：2005-03-24

    申请人： Daniel Gudmunson ,  John Melanson ,  Rahul Singh ,  Ahsan Chowdhury

    发明人： Daniel Gudmunson ,  John Melanson ,  Rahul Singh ,  Ahsan Chowdhury

    IPC分类号： H04L7/00

    CPC分类号： H03L7/0994 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/197

    摘要： A method and apparatus for maintaining an ideal frequency ratio between numerically-controlled frequency sources provides a mechanism for maintaining coherence between multiple synchronization references where a known ideal rational relationship between the sources is known. Multiple numerically controlled oscillators (NCOs) generate the multiple synchronization references, which may be clock signals or numeric phase representations and the outputs of the NCOs are compared with a ratiometric frequency comparator that determines whether there is an error in the ratio between the NCO outputs. The frequency of one of the NCOs is then adjusted with a frequency correction factor provided by the ratiometric frequency comparator. The NCO inputs can represent ratios of the synchronization reference frequencies to a fixed reference clock and the NCOs clocked by the fixed reference clock.

    摘要翻译： 用于在数控频率源之间保持理想频率比的方法和装置提供了一种维持多个同步参考之间的相干性的机制，其中已知的源之间的理想的理性关系是已知的。 多个数控振荡器（NCO）产生多个同步参考，其可以是时钟信号或数字相位表示，并且将NCO的输出与比较率频率比较器进行比较，其确定NCO输出之间的比率是否存在误差。 然后用比例式频率比较器提供的频率校正因子来调整NCO之一的频率。 NCO输入可以表示同步参考频率与固定参考时钟的比率和由固定参考时钟计时的NCO。

    Method and system for synchronizing video information derived from an asynchronously sampled video signal
    6.
    发明授权
    Method and system for synchronizing video information derived from an asynchronously sampled video signal 有权
    用于同步从异步采样的视频信号导出的视频信息的方法和系统

    公开(公告)号：US07499106B1

    公开(公告)日：2009-03-03

    申请号：US11082346

    申请日：2005-03-17

    申请人： Daniel Gudmunson ,  John Melanson ,  Rahul Singh ,  Ahsan Chowdhury

    发明人： Daniel Gudmunson ,  John Melanson ,  Rahul Singh ,  Ahsan Chowdhury

    IPC分类号： H04L7/00

    CPC分类号： H03L7/1974 ,  H03L7/08 ,  H03L7/0805 ,  H03L2207/50 ,  H04N5/12 ,  H04N5/213 ,  H04N5/765 ,  H04N5/85 ,  H04N7/0132 ,  H04N9/8042 ,  H04N9/896 ,  H04N21/4325 ,  H04N21/44004

    摘要： A method and system for synchronizing video information derived from an asynchronously sampled video signals provide a mechanism for using asynchronous sampling in the front-end of digital video capture systems. A ratio between the sampling clock frequency and the source video clock frequency is computed via an all digital phase-lock loop (ADPLL) and either a video clock is generated from the ratio by another PLL, a number to clock converter or the ratio is used directly to provide digital synchronization information to downstream processing blocks. A sample rate converter (SRC) is provided in an interpolator that either acts as a sample position corrector at the same line rate as the received video, or by introducing an offset in the ADPLL, the video data can be converted to another line rate via the SRC.

    摘要翻译： 用于同步从异步采样的视频信号导出的视频信息的方法和系统提供了在数字视频采集系统的前端中使用异步采样的机制。 通过全数字锁相环（ADPLL）计算采样时钟频率和源视频时钟频率之间的比例，并且视频时钟由另一个PLL的比率，数字到时钟转换器或使用的比率产生 直接向下游处理块提供数字同步信息。 在内插器中提供采样率转换器（SRC），其作为采样位置校正器以与接收的视频相同的线路速率，或者通过在ADPLL中引入偏移量，视频数据可以通过 SRC。

    Methods and circuits for implementing programmable gamma correction
    7.
    发明授权
    Methods and circuits for implementing programmable gamma correction 有权
    实现可编程伽玛校正的方法和电路

    公开(公告)号：US07154562B1

    公开(公告)日：2006-12-26

    申请号：US10685128

    申请日：2003-10-14

    申请人： Ahsan Chowdhury ,  Anand Venkitachalam ,  John Melanson

    发明人： Ahsan Chowdhury ,  Anand Venkitachalam ,  John Melanson

    IPC分类号： H04N5/202 ,  H04N9/69

    CPC分类号： H04N5/202

    摘要： A method of gamma correction includes selecting lower and upper reference curves corresponding to selected reference gamma values. A gamma correction curve is generated from a corresponding gamma correction value and cross-correlated with the upper and lower reference curves to generate a corresponding set of cross-correlation factors. The set of cross-correlation factors are stored and indexed to the corresponding gamma value. An input value is received for gamma correction with the corresponding gamma value. Data from the upper and lower reference curves indexed by the input value are then operated one with the cross-correlation factors to generate a gamma corrected output value.

    摘要翻译： 伽马校正的方法包括选择对应于所选参考伽马值的下参考曲线和上参考曲线。 从相应的伽马校正值产生伽马校正曲线，并与上参考曲线和下参考曲线交叉相关，以产生相应的一组互相关因子。 互相关因子的集合被存储并被索引到相应的伽马值。 接收用于具有相应伽马值的伽马校正的输入值。 然后，通过输入值索引的来自上下参考曲线的数据与互相关因子一起运算，以产生伽马校正输出值。

    Single-chip analog to digital video decoder with on-chip vertical blanking interval data slicing during low-power operations
    8.
    发明申请
    Single-chip analog to digital video decoder with on-chip vertical blanking interval data slicing during low-power operations 审中-公开
    单片模拟数字视频解码器，在低功耗操作期间具有片上垂直消隐间隔数据切片

    公开(公告)号：US20060044468A1

    公开(公告)日：2006-03-02

    申请号：US11041582

    申请日：2005-01-24

    申请人： Ahsan Chowdhury ,  James Antone ,  Krishnan Subramoniam

    发明人： Ahsan Chowdhury ,  James Antone ,  Krishnan Subramoniam

    IPC分类号： H04N11/00

    CPC分类号： H04N5/44513 ,  H04N5/63 ,  H04N7/035 ,  H04N7/088

    摘要： A single-chip video decoder includes a primary data path for capturing and slicing vertical blanking interval information carried by a primary channel of video data received by a video decoder. Power control circuitry is operable during an inactive period of the video decoder to activate the primary data path during vertical blanking intervals of the received primary channel of video data for capturing and slicing the vertical blanking interval data; and to deactivate the primary data path between the vertical blanking interval and a subsequent vertical blanking interval of the received primary channel of video data to reduce power consumption. According to further inventive concepts, analog and/or digital circuitry which is unnecessary for capturing and slicing the vertical blanking information, including data paths processing secondary channels of video data, is deactivated during substantially the entire inactive period of the video decoder. In an additional embodiment, the input/output ports of the video decoder are set into a static state for substantially the entire inactive period.

    摘要翻译： 单片视频解码器包括用于捕获和分割由视频解码器接收的视频数据的主要信道携带的垂直消隐间隔信息的主数据路径。 功率控制电路可在视频解码器的非活动时段期间操作，以便在所接收的视频数据主通道的垂直消隐间隔期间激活主要数据路径，用于捕捉和分割垂直消隐间隔数据; 并且停用垂直消隐间隔和所接收的视频数据的主要信道的随后的垂直消隐间隔之间的主数据路径，以减少功耗。 根据另外的发明概念，在视频解码器的基本上整个非活动时段期间，不需要用于捕获和分割垂直消隐信息（包括处理视频数据的次要信道的数据路径）的模拟和/或数字电路。 在另外的实施例中，视频解码器的输入/输出端口在大体上整个非活动期间被设置为静态。