Abstract:
A method and apparatus for process integration in manufacture of a gate structure of a field effect transistor are disclosed. The method includes assembling an integrated substrate processing system having a metrology module and a vacuumed processing platform to perform controlled and adaptive plasma processes without exposing the substrate to a non-vacuumed environment.
Abstract:
A method for etching a chromium layer is provided herein. In one embodiment, a method for etching a chromium layer includes providing a filmstack in an etching chamber, the filmstack having a chromium layer partially exposed through a patterned layer, providing at least one halogen containing process gas to a processing chamber, biasing the layer disposed on a substrate support in the processing chamber with a plurality of power pulses less than 600 Watts, and etching the chromium layer through a patterned mask. The method for plasma etching a chromium layer described herein is particularly suitable for fabricating photomasks.
Abstract:
A method and apparatus for process integration in manufacture of a gate structure of a field effect transistor are disclosed. The method includes assembling an integrated substrate processing system having a metrology module and a vacuumed processing platform to perform controlled and adaptive plasma processes without exposing the substrate to a non-vacuumed environment.
Abstract:
A method and apparatus for process integration in manufacture of a gate structure of a field effect transistor are disclosed. The method includes assembling an integrated substrate processing system having a metrology module and a vacuumed processing platform to perform controlled and adaptive plasma processes without exposing the substrate to a non-vacuumed environment.
Abstract:
A method for etching a chromium layer is provided herein. In one embodiment, a method for etching a chromium layer includes providing a filmstack in an etching chamber, the filmstack having a chromium layer partially exposed through a patterned layer, providing at least one halogen containing process gas to a processing chamber, biasing the layer disposed on a substrate support in the processing chamber with a plurality of power pulses less than 600 Watts, and etching the chromium layer through a patterned mask. The method for plasma etching a chromium layer described herein is particularly suitable for fabricating photomasks.
Abstract:
A method and apparatus for process integration in manufacture of a gate structure of a field effect transistor are disclosed. The method includes assembling an integrated substrate processing system having a metrology module and a vacuumed processing platform to perform controlled and adaptive plasma processes without exposing the substrate to a non-vacuumed environment.
Abstract:
The present invention relates to a additive composition for use as lubricity improver for low sulphur diesel, comprising c) 0.1-10% by weight of ester derivative derived from cashew nut shell liquid (CNSL esters) of formula (I); f) 0.1-10% by weight of ester derivative derived from cashew nut shell liquid of formula (II); g) 50-95% by weight of free fatty acid of the formula RCOOH in which R represents an alkyl/alkenyl group with 12 to 24 carbon atoms. h) 1-30% by weight of synthetic esters derived by esterifying tri, tetra, penta hydric alcohols with carboxylic acids such as lauric, palmitic, linoleic, ricinoleic etc.
Abstract:
The present invention relates to a additive composition for use as lubricity improver for low sulphur diesel, comprising c) 0.1-10% by weight of ester derivative derived from cashew nut shell liquid (CNSL esters) of formula (I); f) 0.1-10% by weight of ester derivative derived from cashew nut shell liquid of formula (II); g) 50-95% by weight of free fatty acid of the formula RCOOH in which R represents an alkyl/alkenyl group with 12 to 24 carbon atoms. h) 1-30% by weight of synthetic esters derived by esterifying tri, tetra, penta hydric alcohols with carboxylic acids such as lauric, palmitic, linoleic, ricinoleic etc.
Abstract:
The disclosure provides compounds and methods for treating cancer by inhibiting the formation of cancer cells resistant to paclitaxel by preventing the formation of GBP1:PIM1 protein interaction during a chemotherapeutic treatment. These compounds and methods are able to treat cancer individually or in conjunction with paclitaxel.
Abstract:
Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer including a plurality of integrated circuits includes forming a water soluble mask above the semiconductor wafer, the water soluble mask covering and protecting the integrated circuits. The method also includes baking the water soluble mask to increase the etch resistance of the water soluble mask. The method also includes, subsequent to baking the water soluble mask, patterning the water soluble mask with a laser scribing process to provide a water soluble patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The method also includes plasma etching the semiconductor wafer through the gaps in the water soluble patterned mask to singulate the integrated circuits.