公开(公告)号：US07893505B2

公开(公告)日：2011-02-22

申请号：US12362995

申请日：2009-01-30

申请人： Akio Nishida ,  Yasuko Yoshida ,  Shuji Ikeda

发明人： Akio Nishida ,  Yasuko Yoshida ,  Shuji Ikeda

IPC分类号： H01L21/8234 ,  H01L21/8244

CPC分类号： H01L27/11 ,  H01L27/1104

摘要： In order to provide a semiconductor integrated circuit device such as a high-performance semiconductor integrated circuit device capable of reducing a soft error developed in each memory cell of a SRAM, the surface of a wiring of a cross-connecting portion, of a SRAM memory cell having a pair of n-channel type MISFETs whose gate electrodes and drains are respectively cross-connected, is formed in a shape that protrudes from the surface of a silicon oxide film. A silicon nitride film used as a capacitive insulating film, and an upper electrode are formed on the wiring. A capacitance can be formed of the wiring, the silicon nitride film and the upper electrode.

摘要翻译： 为了提供一种半导体集成电路器件，例如能够减少在SRAM的每个存储单元中产生的软错误的高性能半导体集成电路器件，SRAM存储器的交叉连接部分的布线表面 其栅电极和漏极分别交叉连接的一对n沟道型MISFET形成为从氧化硅膜的表面突出的形状。 在布线上形成用作电容绝缘膜的氮化硅膜和上电极。 电容可以由布线，氮化硅膜和上电极形成。

公开(公告)号：US20060128094A1

公开(公告)日：2006-06-15

申请号：US11342695

申请日：2006-01-31

申请人： Akio Nishida ,  Yasuko Yoshida ,  Shuji Ikeda

发明人： Akio Nishida ,  Yasuko Yoshida ,  Shuji Ikeda

IPC分类号： H01L21/8242

CPC分类号： H01L27/11 ,  H01L27/1104

摘要： In order to provide a semiconductor integrated circuit device such as a high-performance semiconductor integrated circuit device capable of reducing a soft error developed in each memory cell of a SRAM, the surface of a wiring of a cross-connecting portion, of a SRAM memory cell having a pair of n-channel type MISFETs whose gate electrodes and drains are respectively cross-connected, is formed in a shape that protrudes from the surface of a silicon oxide film. A silicon nitride film used as a capacitive insulating film, and an upper electrode are formed on the wiring. A capacitance can be formed of the wiring, the silicon nitride film and the upper electrode.

摘要翻译： 为了提供一种半导体集成电路器件，例如能够减少在SRAM的每个存储单元中产生的软错误的高性能半导体集成电路器件，SRAM存储器的交叉连接部分的布线表面 其栅电极和漏极分别交叉连接的一对n沟道型MISFET形成为从氧化硅膜的表面突出的形状。 在布线上形成用作电容绝缘膜的氮化硅膜和上电极。 电容可以由布线，氮化硅膜和上电极形成。

公开(公告)号：US07488639B2

公开(公告)日：2009-02-10

申请号：US11342695

申请日：2006-01-31

申请人： Akio Nishida ,  Yasuko Yoshida ,  Shuji Ikeda

发明人： Akio Nishida ,  Yasuko Yoshida ,  Shuji Ikeda

IPC分类号： H01L21/8238

CPC分类号： H01L27/11 ,  H01L27/1104

摘要： In order to provide a semiconductor integrated circuit device such as a high-performance semiconductor integrated circuit device capable of reducing a soft error developed in each memory cell of a SRAM, the surface of a wiring of a cross-connecting portion, of a SRAM memory cell having a pair of n-channel type MISFETs whose gate electrodes and drains are respectively cross-connected, is formed in a shape that protrudes from the surface of a silicon oxide film. A silicon nitride film used as a capacitive insulating film, and an upper electrode are formed on the wiring. A capacitance can be formed of the wiring, the silicon nitride film and the upper electrode.

摘要翻译： 为了提供一种半导体集成电路器件，例如能够减少在SRAM的每个存储单元中产生的软错误的高性能半导体集成电路器件，SRAM存储器的交叉连接部分的布线表面 其栅电极和漏极分别交叉连接的一对n沟道型MISFET形成为从氧化硅膜的表面突出的形状。 在布线上形成用作电容绝缘膜的氮化硅膜和上电极。 电容可以由布线，氮化硅膜和上电极形成。

公开(公告)号：US07067864B2

公开(公告)日：2006-06-27

申请号：US10363055

申请日：2001-12-26

申请人： Akio Nishida ,  Yasuko Yoshida ,  Shuji Ikeda

发明人： Akio Nishida ,  Yasuko Yoshida ,  Shuji Ikeda

IPC分类号： H01L27/108

CPC分类号： H01L27/11 ,  H01L27/1104

摘要： In order to provide a semiconductor integrated circuit device such as a high-performance semiconductor integrated circuit device capable of reducing a soft error developed in each memory cell of a SRAM, the surface of a wiring of a cross-connecting portion, of a SRAM memory cell having a pair of n-channel type MISFETs whose gate electrodes and drains are respectively cross-connected, is formed in a shape that protrudes from the surface of a silicon oxide film. A silicon nitride film used as a capacitive insulating film, and an upper electrode are formed on the wiring. A capacitance can be formed of the wiring, the silicon nitride film and the upper electrode.

摘要翻译： 为了提供一种半导体集成电路器件，例如能够减少在SRAM的每个存储单元中产生的软错误的高性能半导体集成电路器件，SRAM存储器的交叉连接部分的布线表面 其栅电极和漏极分别交叉连接的一对n沟道型MISFET形成为从氧化硅膜的表面突出的形状。 在布线上形成用作电容绝缘膜的氮化硅膜和上电极。 电容可以由布线，氮化硅膜和上电极形成。

公开(公告)号：US06677194B2

公开(公告)日：2004-01-13

申请号：US10162573

申请日：2002-06-06

申请人： Toshiaki Yamanaka ,  Akio Nishida ,  Yasuko Yoshida ,  Shuji Ikeda ,  Kenichi Kuroda ,  Shiro Kamohara ,  Shinichiro Kimura ,  Eiichi Murakami ,  Hideyuki Matsuoka ,  Masataka Minami

发明人： Toshiaki Yamanaka ,  Akio Nishida ,  Yasuko Yoshida ,  Shuji Ikeda ,  Kenichi Kuroda ,  Shiro Kamohara ,  Shinichiro Kimura ,  Eiichi Murakami ,  Hideyuki Matsuoka ,  Masataka Minami

IPC分类号： H01L218238

CPC分类号： H01L21/823807 ,  H01L21/2652 ,  H01L21/823842 ,  H01L21/823892

摘要： A low threshold voltage NMIS area and a high threshold voltage PMIS area are set by a photoresist mask also used for well formation. Using a photoresist mask with openings for the NMIS and PMIS, the NMIS and PMIS areas are set by one ion implantation step. After gate oxidation, ion implantation is conducted through an amorphous silicon film onto wells, channels, and gate electrodes. A plurality of CMIS threshold voltages can be set and the gate electrodes of both polarities can be formed in a reduced number of steps using photoresist. This solves the problem in which photomasks are required as many as there are ion implantation types for wells, channel stoppers, gate electrodes, and threshold voltage control and hence the number of manufacturing steps and the production cost are increased.

摘要翻译： 低阈值电压NMIS区域和高阈值电压PMIS区域由也用于阱形成的光致抗蚀剂掩模设置。 使用具有用于NMIS和PMIS的开口的光致抗蚀剂掩模，通过一个离子注入步骤设置NMIS和PMIS区域。 栅极氧化后，离子注入通过非晶硅膜导入孔，通道和栅电极。 可以设置多个CMIS阈值电压，并且可以以减少数量的步骤使用光致抗蚀剂形成两个极性的栅电极。 这解决了需要光掩模的问题，因为存在孔，通道阻挡件，栅电极和阈值电压控制的离子注入类型，因此制造步骤的数量和生产成本增加。

公开(公告)号：US20090218608A1

公开(公告)日：2009-09-03

申请号：US12362995

申请日：2009-01-30

申请人： Akio NISHIDA ,  Yasuko Yoshida ,  Shuji Ikeda

发明人： Akio NISHIDA ,  Yasuko Yoshida ,  Shuji Ikeda

IPC分类号： H01L27/11

CPC分类号： H01L27/11 ,  H01L27/1104

摘要： In order to provide a semiconductor integrated circuit device such as a high-performance semiconductor integrated circuit device capable of reducing a soft error developed in each memory cell of a SRAM, the surface of a wiring of a cross-connecting portion, of a SRAM memory cell having a pair of n-channel type MISFETs whose gate electrodes and drains are respectively cross-connected, is formed in a shape that protrudes from the surface of a silicon oxide film. A silicon nitride film used as a capacitive insulating film, and an upper electrode are formed on the wiring. A capacitance can be formed of the wiring, the silicon nitride film and the upper electrode.

摘要翻译： 为了提供一种半导体集成电路器件，例如能够减少在SRAM的每个存储单元中产生的软错误的高性能半导体集成电路器件，SRAM存储器的交叉连接部分的布线表面 其栅电极和漏极分别交叉连接的一对n沟道型MISFET形成为从氧化硅膜的表面突出的形状。 在布线上形成用作电容绝缘膜的氮化硅膜和上电极。 电容可以由布线，氮化硅膜和上电极形成。

公开(公告)号：US07402473B2

公开(公告)日：2008-07-22

申请号：US11108827

申请日：2005-04-19

申请人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Norio Suzuki ,  Yasushi Matsuda ,  Yasuko Yoshida ,  Hirohiko Yamamoto ,  Masamichi Kobayashi ,  Akira Takamatsu ,  Hirofumi Shimizu ,  Kazushi Fukuda ,  Shinichi Horibe ,  Toshio Nozoe

发明人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Norio Suzuki ,  Yasushi Matsuda ,  Yasuko Yoshida ,  Hirohiko Yamamoto ,  Masamichi Kobayashi ,  Akira Takamatsu ,  Hirofumi Shimizu ,  Kazushi Fukuda ,  Shinichi Horibe ,  Toshio Nozoe

IPC分类号： H01L21/336 ,  H01L21/76

CPC分类号： H01L21/76232 ,  H01L21/76235 ,  H01L29/78

摘要： A process of producing a semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step. The device is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.

摘要翻译： 一种制造半导体器件的方法，该半导体器件具有高度可靠的凹槽隔离结构，其具有在凹槽上边缘处形成的所需曲率半径，并且不形成任何步骤。 通过减小半导体基板上的元件隔离槽的槽上缘周围的应力产生，从而优化元件隔离槽的形状并使器件更细，并提高器件电特性来制造器件。

公开(公告)号：US06713353B1

公开(公告)日：2004-03-30

申请号：US09536756

申请日：2000-03-28

申请人： Takayuki Kanda ,  Atsushi Hiraiwa ,  Norio Suzuki ,  Satoshi Sakai ,  Shuji Ikeda ,  Yasuko Yoshida ,  Shinichi Horibe

发明人： Takayuki Kanda ,  Atsushi Hiraiwa ,  Norio Suzuki ,  Satoshi Sakai ,  Shuji Ikeda ,  Yasuko Yoshida ,  Shinichi Horibe

IPC分类号： H01L218234

CPC分类号： H01L21/823878 ,  H01L21/823857

摘要： A protection film is formed on a silicon oxide film 6 formed on the surface of a semiconductor substrate, a silicon oxide film is removed from a region where a thin gate-insulating film is to be formed by using, as a mask, a photoresist pattern that covers a region where a thick gate-insulating film is to be formed, and, then, the photoresist pattern is removed followed by washing. Then, the semiconductor substrate is heat-oxidized or a film is deposited thereon to form gate-insulating films having different thicknesses.

公开(公告)号：US06562695B1

公开(公告)日：2003-05-13

申请号：US09889018

申请日：2001-07-10

申请人： Norio Suzuki ,  Hiroyuki Ichizoe ,  Masayuki Kojima ,  Keiji Okamoto ,  Shinichi Horibe ,  Kozo Watanabe ,  Yasuko Yoshida ,  Shuji Ikeda ,  Akira Takamatsu ,  Norio Ishitsuka ,  Atsushi Ogishima ,  Maki Shimoda

发明人： Norio Suzuki ,  Hiroyuki Ichizoe ,  Masayuki Kojima ,  Keiji Okamoto ,  Shinichi Horibe ,  Kozo Watanabe ,  Yasuko Yoshida ,  Shuji Ikeda ,  Akira Takamatsu ,  Norio Ishitsuka ,  Atsushi Ogishima ,  Maki Shimoda

IPC分类号： H01L2176

CPC分类号： H01L21/76229 ,  H01L21/76224 ,  H01L21/76232 ,  H01L27/10852 ,  H01L28/91

摘要： Grooves are defined in a substrate having device isolation regions by dry etching using silicon nitride films and side wall spacers as masks. Thereafter, the side wall spacers lying on side walls of the silicon nitride films are removed and the substrate is subjected to thermal oxidation, whereby the surface of the substrate at a peripheral portion of each active region is subjected to so-called round processing so as to have a sectional shape having a convex rounded shape.

摘要翻译： 通过使用氮化硅膜和侧壁间隔物作为掩模的干蚀刻将沟槽限定在具有器件隔离区的衬底中。 此后，除去位于氮化硅膜侧壁上的侧壁隔离物，并对衬底进行热氧化，由此在每个有源区的周边部分的衬底表面进行所谓的圆形处理，以便 具有凸形圆形的截面形状。

公开(公告)号：US06242323B1

公开(公告)日：2001-06-05

申请号：US09367524

申请日：1999-08-16

申请人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Norio Suzuki ,  Yasushi Matsuda ,  Yasuko Yoshida ,  Hirohiko Yamamoto ,  Masamichi Kobayashi ,  Akira Takamatsu ,  Hirofumi Shimizu ,  Kazushi Fukuda ,  Shinichi Horibe ,  Toshio Nozoe

发明人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Norio Suzuki ,  Yasushi Matsuda ,  Yasuko Yoshida ,  Hirohiko Yamamoto ,  Masamichi Kobayashi ,  Akira Takamatsu ,  Hirofumi Shimizu ,  Kazushi Fukuda ,  Shinichi Horibe ,  Toshio Nozoe

IPC分类号： H01L2176

CPC分类号： H01L21/76232 ,  H01L21/76235 ,  H01L29/78

摘要： A semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step, there is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.

摘要翻译： 一种半导体器件，其具有高度可靠的凹槽隔离结构，其具有在凹槽上边缘处形成的所需曲率半径，并且不形成任何步骤，通过减小半导体上的元件隔离槽的沟槽上边缘周围的应力产生而产生 从而优化元件隔离槽的形状并使器件更精细并提高器件的电气特性。