公开(公告)号：US07893505B2

公开(公告)日：2011-02-22

申请号：US12362995

申请日：2009-01-30

申请人： Akio Nishida ,  Yasuko Yoshida ,  Shuji Ikeda

发明人： Akio Nishida ,  Yasuko Yoshida ,  Shuji Ikeda

IPC分类号： H01L21/8234 ,  H01L21/8244

CPC分类号： H01L27/11 ,  H01L27/1104

摘要： In order to provide a semiconductor integrated circuit device such as a high-performance semiconductor integrated circuit device capable of reducing a soft error developed in each memory cell of a SRAM, the surface of a wiring of a cross-connecting portion, of a SRAM memory cell having a pair of n-channel type MISFETs whose gate electrodes and drains are respectively cross-connected, is formed in a shape that protrudes from the surface of a silicon oxide film. A silicon nitride film used as a capacitive insulating film, and an upper electrode are formed on the wiring. A capacitance can be formed of the wiring, the silicon nitride film and the upper electrode.

摘要翻译： 为了提供一种半导体集成电路器件，例如能够减少在SRAM的每个存储单元中产生的软错误的高性能半导体集成电路器件，SRAM存储器的交叉连接部分的布线表面 其栅电极和漏极分别交叉连接的一对n沟道型MISFET形成为从氧化硅膜的表面突出的形状。 在布线上形成用作电容绝缘膜的氮化硅膜和上电极。 电容可以由布线，氮化硅膜和上电极形成。

公开(公告)号：US20060128094A1

公开(公告)日：2006-06-15

申请号：US11342695

申请日：2006-01-31

申请人： Akio Nishida ,  Yasuko Yoshida ,  Shuji Ikeda

发明人： Akio Nishida ,  Yasuko Yoshida ,  Shuji Ikeda

IPC分类号： H01L21/8242

CPC分类号： H01L27/11 ,  H01L27/1104

摘要： In order to provide a semiconductor integrated circuit device such as a high-performance semiconductor integrated circuit device capable of reducing a soft error developed in each memory cell of a SRAM, the surface of a wiring of a cross-connecting portion, of a SRAM memory cell having a pair of n-channel type MISFETs whose gate electrodes and drains are respectively cross-connected, is formed in a shape that protrudes from the surface of a silicon oxide film. A silicon nitride film used as a capacitive insulating film, and an upper electrode are formed on the wiring. A capacitance can be formed of the wiring, the silicon nitride film and the upper electrode.

摘要翻译： 为了提供一种半导体集成电路器件，例如能够减少在SRAM的每个存储单元中产生的软错误的高性能半导体集成电路器件，SRAM存储器的交叉连接部分的布线表面 其栅电极和漏极分别交叉连接的一对n沟道型MISFET形成为从氧化硅膜的表面突出的形状。 在布线上形成用作电容绝缘膜的氮化硅膜和上电极。 电容可以由布线，氮化硅膜和上电极形成。

公开(公告)号：US07488639B2

公开(公告)日：2009-02-10

申请号：US11342695

申请日：2006-01-31

申请人： Akio Nishida ,  Yasuko Yoshida ,  Shuji Ikeda

发明人： Akio Nishida ,  Yasuko Yoshida ,  Shuji Ikeda

IPC分类号： H01L21/8238

CPC分类号： H01L27/11 ,  H01L27/1104

摘要： In order to provide a semiconductor integrated circuit device such as a high-performance semiconductor integrated circuit device capable of reducing a soft error developed in each memory cell of a SRAM, the surface of a wiring of a cross-connecting portion, of a SRAM memory cell having a pair of n-channel type MISFETs whose gate electrodes and drains are respectively cross-connected, is formed in a shape that protrudes from the surface of a silicon oxide film. A silicon nitride film used as a capacitive insulating film, and an upper electrode are formed on the wiring. A capacitance can be formed of the wiring, the silicon nitride film and the upper electrode.

摘要翻译： 为了提供一种半导体集成电路器件，例如能够减少在SRAM的每个存储单元中产生的软错误的高性能半导体集成电路器件，SRAM存储器的交叉连接部分的布线表面 其栅电极和漏极分别交叉连接的一对n沟道型MISFET形成为从氧化硅膜的表面突出的形状。 在布线上形成用作电容绝缘膜的氮化硅膜和上电极。 电容可以由布线，氮化硅膜和上电极形成。

公开(公告)号：US07067864B2

公开(公告)日：2006-06-27

申请号：US10363055

申请日：2001-12-26

申请人： Akio Nishida ,  Yasuko Yoshida ,  Shuji Ikeda

发明人： Akio Nishida ,  Yasuko Yoshida ,  Shuji Ikeda

IPC分类号： H01L27/108

CPC分类号： H01L27/11 ,  H01L27/1104

摘要： In order to provide a semiconductor integrated circuit device such as a high-performance semiconductor integrated circuit device capable of reducing a soft error developed in each memory cell of a SRAM, the surface of a wiring of a cross-connecting portion, of a SRAM memory cell having a pair of n-channel type MISFETs whose gate electrodes and drains are respectively cross-connected, is formed in a shape that protrudes from the surface of a silicon oxide film. A silicon nitride film used as a capacitive insulating film, and an upper electrode are formed on the wiring. A capacitance can be formed of the wiring, the silicon nitride film and the upper electrode.

摘要翻译： 为了提供一种半导体集成电路器件，例如能够减少在SRAM的每个存储单元中产生的软错误的高性能半导体集成电路器件，SRAM存储器的交叉连接部分的布线表面 其栅电极和漏极分别交叉连接的一对n沟道型MISFET形成为从氧化硅膜的表面突出的形状。 在布线上形成用作电容绝缘膜的氮化硅膜和上电极。 电容可以由布线，氮化硅膜和上电极形成。

公开(公告)号：US06677194B2

公开(公告)日：2004-01-13

申请号：US10162573

申请日：2002-06-06

申请人： Toshiaki Yamanaka ,  Akio Nishida ,  Yasuko Yoshida ,  Shuji Ikeda ,  Kenichi Kuroda ,  Shiro Kamohara ,  Shinichiro Kimura ,  Eiichi Murakami ,  Hideyuki Matsuoka ,  Masataka Minami

发明人： Toshiaki Yamanaka ,  Akio Nishida ,  Yasuko Yoshida ,  Shuji Ikeda ,  Kenichi Kuroda ,  Shiro Kamohara ,  Shinichiro Kimura ,  Eiichi Murakami ,  Hideyuki Matsuoka ,  Masataka Minami

IPC分类号： H01L218238

CPC分类号： H01L21/823807 ,  H01L21/2652 ,  H01L21/823842 ,  H01L21/823892

摘要： A low threshold voltage NMIS area and a high threshold voltage PMIS area are set by a photoresist mask also used for well formation. Using a photoresist mask with openings for the NMIS and PMIS, the NMIS and PMIS areas are set by one ion implantation step. After gate oxidation, ion implantation is conducted through an amorphous silicon film onto wells, channels, and gate electrodes. A plurality of CMIS threshold voltages can be set and the gate electrodes of both polarities can be formed in a reduced number of steps using photoresist. This solves the problem in which photomasks are required as many as there are ion implantation types for wells, channel stoppers, gate electrodes, and threshold voltage control and hence the number of manufacturing steps and the production cost are increased.

摘要翻译： 低阈值电压NMIS区域和高阈值电压PMIS区域由也用于阱形成的光致抗蚀剂掩模设置。 使用具有用于NMIS和PMIS的开口的光致抗蚀剂掩模，通过一个离子注入步骤设置NMIS和PMIS区域。 栅极氧化后，离子注入通过非晶硅膜导入孔，通道和栅电极。 可以设置多个CMIS阈值电压，并且可以以减少数量的步骤使用光致抗蚀剂形成两个极性的栅电极。 这解决了需要光掩模的问题，因为存在孔，通道阻挡件，栅电极和阈值电压控制的离子注入类型，因此制造步骤的数量和生产成本增加。

公开(公告)号：US06897499B2

公开(公告)日：2005-05-24

申请号：US10359678

申请日：2003-02-07

申请人： Akio Nishida ,  Noriyuki Yabuoshi ,  Yasuko Yoshida ,  Kazuhiro Komori ,  Sousuke Tsuji ,  Hideo Miwa ,  Mitsuhiro Higuchi ,  Koichi Imato

发明人： Akio Nishida ,  Noriyuki Yabuoshi ,  Yasuko Yoshida ,  Kazuhiro Komori ,  Sousuke Tsuji ,  Hideo Miwa ,  Mitsuhiro Higuchi ,  Koichi Imato

IPC分类号： H01L21/8234 ,  G11C11/412 ,  H01L21/335 ,  H01L21/8244 ,  H01L27/088 ,  H01L27/105 ,  H01L27/11 ,  H01L29/423 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L27/11 ,  G11C11/412 ,  H01L27/105 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/4238

摘要： A gate electrode of each MISFET is formed on a substrate in an active region whose periphery is defined by an element isolation trench, and crosses the active region so as to extend from one end thereof to the other end thereof. The gate electrode has a gate length in a boundary region defined between the active region and the element isolation trench which is greater than a gate length in a central portion of the active region. The gate electrode is configured in an H-type flat pattern. Further, the gate electrode covers the whole of one side extending along a gate-length direction, of the boundary region defined between the active region L and the element isolation trench, and parts of two sides thereof extending along a gate-width direction. The MISFETs are formed in electrically separated wells and are connected in series to constitute part of a reference voltage generating circuit.

摘要翻译： 每个MISFET的栅电极形成在其周围由元件隔离沟槽限定的有源区中的衬底上，并且穿过有源区从其一端延伸到另一端。 栅极电极在有源区域和元件隔离沟槽之间限定的边界区域中的栅极长度大于有源区域的中心部分中的栅极长度。 栅电极配置为H型平面图案。 此外，栅电极覆盖沿着栅极长度方向延伸的整个一侧，限定在有源区域L和元件隔离沟槽之间的边界区域以及沿栅极宽度方向延伸的两侧的部分。 MISFET形成在电分离的阱中并且串联连接以构成参考电压产生电路的一部分。

公开(公告)号：US07045864B2

公开(公告)日：2006-05-16

申请号：US10170432

申请日：2002-06-14

申请人： Kota Funayama ,  Yasuko Yoshida ,  Masaru Nakamichi ,  Akio Nishida

发明人： Kota Funayama ,  Yasuko Yoshida ,  Masaru Nakamichi ,  Akio Nishida

IPC分类号： H01L29/76

CPC分类号： H01L27/11 ,  H01L21/823814 ,  H01L21/823835 ,  H01L27/092 ,  H01L27/1104 ,  Y10S257/903 ,  Y10S257/904

摘要： A semiconductor integrated circuit device, e.g., a memory cell of an SRAM, is formed of a pair of inverters having their input and output points connected in a crisscross manner and being formed of drive n-channel MISFETs and load p-channel MISFETs. The n-channel MISFETs and p-channel MISFETs have their back gates supplied with power supply voltage and a ground voltage, respectively. The MISFETs are formed with a metal silicide layer on the gate electrodes G and source regions (hatched areas) and without the formation of a metal silicide layer on the drain regions, respectively, whereby the leakage current of the MISFETs due to a voltage difference between the drain regions and wells can be reduced, and, thus, the power consumption can be reduced.

摘要翻译： 诸如SRAM的存储单元的半导体集成电路器件由一对反相器形成，它们的输入和输出点以十字交叉的方式连接并且由驱动n沟道MISFET和负载p沟道MISFET形成。 n沟道MISFET和p沟道MISFET分别具有电源电压和接地电压的后门。 MISFET在栅极电极G和源极区域（阴影区域）上形成有金属硅化物层，并且在漏极区域上不形成金属硅化物层，由此由于MISFET的漏电流由于 可以减少漏区和阱，从而可以降低功耗。

公开(公告)号：US06586807B2

公开(公告)日：2003-07-01

申请号：US09774717

申请日：2001-02-01

申请人： Akio Nishida ,  Noriyuki Yabuoshi ,  Yasuko Yoshida ,  Kazuhiro Komori ,  Sousuke Tsuji ,  Hideo Miwa ,  Mitsuhiro Higuchi ,  Koichi Imato

发明人： Akio Nishida ,  Noriyuki Yabuoshi ,  Yasuko Yoshida ,  Kazuhiro Komori ,  Sousuke Tsuji ,  Hideo Miwa ,  Mitsuhiro Higuchi ,  Koichi Imato

IPC分类号： H01L2976

CPC分类号： H01L27/11 ,  G11C11/412 ,  H01L27/105 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/4238

摘要： A gate electrode of each MISFET is formed on a substrate in an active region whose periphery is defined by an element isolation trench, and crosses the active region so as to extend from one end thereof to the other end thereof. The gate electrode has a gate length in a boundary region defined between the active region and the element isolation trench which is greater than a gate length in a central portion of the active region. The gate electrode is configured in an H-type flat pattern. Further, the gate electrode covers the whole of one side extending along a gate-length direction, of the boundary region defined between the active region L and the element isolation trench, and parts of two sides thereof extending along a gate-width direction. The MISFETs are formed in electrically separated wells and are connected in series to constitute part of a reference voltage generating circuit.

摘要翻译： 每个MISFET的栅电极形成在其周围由元件隔离沟槽限定的有源区中的衬底上，并且穿过有源区从其一端延伸到另一端。 栅极电极在有源区域和元件隔离沟槽之间限定的边界区域中的栅极长度大于有源区域的中心部分中的栅极长度。 栅电极配置为H型平面图案。 此外，栅电极覆盖沿着栅极长度方向延伸的整个一侧，限定在有源区域L和元件隔离沟槽之间的边界区域以及沿栅极宽度方向延伸的两侧的部分。 MISFET形成在电分离的阱中并且串联连接以构成参考电压产生电路的一部分。

公开(公告)号：US07972920B2

公开(公告)日：2011-07-05

申请号：US12700344

申请日：2010-02-04

申请人： Hiraku Chakihara ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Makoto Mizuno ,  Keiji Okamoto ,  Mitsuhiro Noguchi ,  Tadanori Yoshida ,  Yasuhiko Takahshi ,  Akio Nishida

发明人： Hiraku Chakihara ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Makoto Mizuno ,  Keiji Okamoto ,  Mitsuhiro Noguchi ,  Tadanori Yoshida ,  Yasuhiko Takahshi ,  Akio Nishida

IPC分类号： H01L21/8244 ,  G11C11/40

CPC分类号： H01L29/6675 ,  H01L21/823885 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/7833 ,  H01L29/78642

摘要： Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.

摘要翻译： 垂直MISFET形成在驱动MISFET和传输MISFET上。 垂直MISFET包括通过层叠下半导体层（漏极），中间半导体层和上半导体层（源极）形成的矩形柱层叠体以及在层叠体的相应侧壁上形成有栅极绝缘膜的栅电极 插入其间。 在每个垂直MISFET中，下半导体层构成漏极，中间半导体层构成衬底（沟道区），上半导体层构成源极。 下半导体层，中间半导体层和上半导体层均由硅膜构成。 下半导体层和上半导体层掺杂有p型并由p型硅膜构成。

公开(公告)号：US07402475B2

公开(公告)日：2008-07-22

申请号：US11265292

申请日：2005-11-03

申请人： Hiraku Chakihara ,  Mitsuhiro Noguchi ,  Masahiro Tadokoro ,  Naonori Wada ,  Akio Nishida

发明人： Hiraku Chakihara ,  Mitsuhiro Noguchi ,  Masahiro Tadokoro ,  Naonori Wada ,  Akio Nishida

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L27/1104 ,  H01L27/11

摘要： In forming five trenches buried with an intermediate conductive layer for connecting transfer MISFETs and driving MISFETs with vertical MISFETs formed thereover, in which the second and third trenches, and the first, fourth, and fifth trenches are formed separately by twice etching using first and second photoresist films as a mask. Since all the trenches can be formed at a good accuracy even in a case where the shortest distance between the first trench and the second or third trench, and the shortest distance between the second or third trench and the fourth trench is smaller than the resolution limit for the exposure light, the distance between each of the five trenches arranged in one identical memory cell can be reduced to be smaller than resolution limit for the exposure light.

摘要翻译： 在形成五个埋入中间导电层的沟槽中，用于连接转移MISFET和驱动MISFET与其上形成的垂直MISFET，其中第二和第三沟槽以及第一，第四和第五沟槽分别通过使用第一和第二 光刻胶膜作为掩模。 由于即使在第一沟槽和第二或第三沟槽之间的最短距离以及第二沟槽和第三沟槽与第四沟槽之间的最短距离小于分辨率极限的情况下，也可以以高精度形成所有沟槽 对于曝光光，布置在一个相同存储单元中的五个沟槽中的每一个之间的距离可以减小到小于曝光光的分辨率极限。