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201 条记录 (耗时 0.022 秒)

    Semiconductor device and method of manufacturing the same
    3.
    发明授权
    Semiconductor device and method of manufacturing the same 失效
    半导体装置及其制造方法

    公开(公告)号：US06727552B2

    公开(公告)日：2004-04-27

    申请号：US10062462

    申请日：2002-02-05

    申请人： Yasuo Inoue ,  Tadashi Nishimura ,  Yasuo Yamaguchi ,  Toshiaki Iwamatsu

    发明人： Yasuo Inoue ,  Tadashi Nishimura ,  Yasuo Yamaguchi ,  Toshiaki Iwamatsu

    IPC分类号： H01L2701

    CPC分类号： H01L21/8238 ,  H01L21/84 ,  H01L23/4825 ,  H01L27/0921 ,  H01L27/1203 ,  H01L29/78609 ,  H01L29/78612 ,  H01L29/78615 ,  H01L29/78621 ,  H01L29/78645 ,  H01L29/78654 ,  H01L2924/0002 ,  H01L2924/00

    摘要： According to a semiconductor device of the present invention, a field oxide film is formed so as to cover the main surface of an SOI layer and to reach the main surface of a buried oxide film. As a result, a pMOS active region of the SOI and an nMOS active region of the SOI can be electrically isolated completely. Therefore, latchup can be prevented completely. As a result, it is possible to provide a semiconductor device using an SOI substrate which can implement high integration by eliminating reduction of the breakdown voltage between source and drain, which was a problem of a conventional SOI field effect transistor, as well as by efficiently disposing a body contact region, which hampers high integration, and a method of manufacturing the same.

    摘要翻译： 根据本发明的半导体器件，形成场致氧化膜以覆盖SOI层的主表面并到达掩埋氧化膜的主表面。 结果，可以完全电隔离SOI的pMOS有源区和SOI的nMOS有源区。 因此，可以完全防止闭锁。 结果，可以提供使用SOI衬底的半导体器件，该SOI衬底可以通过消除源极和漏极之间的击穿电压的降低来实现高集成度，这是常规SOI场效应晶体管的问题，以及有效地 设置妨碍高集成度的身体接触区域及其制造方法。

    Method of manufacturing semiconductor crystalline layer
    6.
    发明授权
    Method of manufacturing semiconductor crystalline layer 失效
    半导体晶体层的制造方法

    公开(公告)号：US4861418A

    公开(公告)日：1989-08-29

    申请号：US22402

    申请日：1987-03-06

    申请人： Tadashi Nishimura ,  Yasuo Inoue ,  Kazuyuki Sugahara ,  Shigeru Kusunoki

    发明人： Tadashi Nishimura ,  Yasuo Inoue ,  Kazuyuki Sugahara ,  Shigeru Kusunoki

    IPC分类号： H01L21/20 ,  H01L21/263 ,  H01L21/268 ,  H01L21/762 ,  H01L29/04

    CPC分类号： H01L29/045 ,  H01L21/2026 ,  H01L21/268 ,  H01L21/76248 ,  Y10S117/904

    摘要： A method of manufacturing a semiconductor crystalline layer comprising the following steps: a step of forming, on a single crystalline substrate composed of a semiconductor having a main face on face and having a diamond-type crystal structure, an orientation flat face in which the direction of the intersection with the main face makes a predetermined angle relative to the direction on the main face and which serves as a reference for defining the direction of arranging semiconductor chips formed on the substrate; a step of forming, on the main face of the substrate, an insulation layer at least a portion of which has an opening reaching the main face and which insulates the substrate at the region other than the opening; a step of forming a semiconductor layer composed of a polycrystalline or amorphous semiconductor on the surface of the opening and the insulation layer; a step of forming a reflectivity varying layer which is in the direction in parallel with or vertical to the intersection between the orientation flat face and the main face, has the width and the distance in a predetermined period and is set so as to show periodical reflectivity variation to the argon laser beams; and a step of scanning the argon laser beams under continuous irradiation by way of the reflectivity varying layer to the semiconductor layer in the direction identical with or at an angle within a certain permissible range to the direction of the main face or the direction equivalent thereto.

    摘要翻译： 一种制造半导体结晶层的方法，包括以下步骤：在由具有主面的具有金刚石型晶体结构的半导体构成的单晶衬底上形成取向平面 其与主面的交点的方向相对于主面上的方向<110>成预定角度，并且作为用于限定形成在基板上的半导体芯片的排列方向的基准; 在所述基板的主面上形成绝缘层的步骤，所述绝缘层的至少一部分具有到达所述主面的开口，并且使所述基板与所述开口以外的区域绝缘; 在开口和绝缘层的表面上形成由多晶或非晶半导体构成的半导体层的步骤; 在与定向平面和主面之间的交叉部分平行或垂直的方向上形成反射率变化层的步骤具有在预定时间段内的宽度和距离，并且被设置为显示周期性反射率 对氩激光束的变化; 以及通过所述反射率变化层在与所述主面或所述主面的方向<110>的一定允许范围内相同或成一定角度的方向将所述氩激光束扫描到所述半导体层的步骤 相当于此。

    Thin film field effect element having an LDD structure
    7.
    发明授权
    Thin film field effect element having an LDD structure 失效
    具有LDD结构的薄膜场效应元件

    公开(公告)号：US5283455A

    公开(公告)日：1994-02-01

    申请号：US911582

    申请日：1992-07-10

    申请人： Yasuo Inoue ,  Tadashi Nishimura ,  Motoi Ashida

    发明人： Yasuo Inoue ,  Tadashi Nishimura ,  Motoi Ashida

    IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/786 ,  H01L29/76 ,  H01L27/01 ,  H01L29/94 ,  H01L31/062

    CPC分类号： H01L29/6675 ,  H01L29/66765 ,  H01L29/78624 ,  H01L29/78642

    摘要： An upper insulating layer is formed on an upper surface of a gate electrode formed on an insulating substrate. A gate insulating layer is formed on sidewalls of the gate electrode and the surfaces of the upper insulating layer. A semiconductor layer is formed on the surfaces of the gate insulating layer. Three source/drain regions are formed in the semiconductor layer. Two independent channel regions are formed in the semiconductor layer along both side surfaces of the gate electrode. Source/drain regions are arranged on both ends of two channel regions. Each source/drain region has an LDD structure formed in a self alignment manner by an oblique ion implantation method and a vertical ion implantation method using sidewall insulating layers formed on the channel regions as masks.

    摘要翻译： 在绝缘基板上形成的栅电极的上表面上形成上绝缘层。 栅极绝缘层形成在栅电极的侧壁和上绝缘层的表面上。 在栅极绝缘层的表面上形成半导体层。 在半导体层中形成三个源/漏区。 沿着栅电极的两个侧表面在半导体层中形成两个独立的沟道区。 源极/漏极区域布置在两个沟道区域的两端。 每个源极/漏极区域具有通过倾斜离子注入方法以自对准方式形成的LDD结构和使用在沟道区上形成的侧壁绝缘层作为掩模的垂直离子注入方法。

    Stacked semiconductor device
    8.
    发明授权
    Stacked semiconductor device 失效
    堆叠半导体器件

    公开(公告)号：US5128732A

    公开(公告)日：1992-07-07

    申请号：US199439

    申请日：1988-05-27

    申请人： Kazuyuki Sugahara ,  Tadashi Nishimura ,  Shigeru Kusunoki ,  Yasuo Inoue ,  Yasuo Yamaguchi

    发明人： Kazuyuki Sugahara ,  Tadashi Nishimura ,  Shigeru Kusunoki ,  Yasuo Inoue ,  Yasuo Yamaguchi

    IPC分类号： H01L27/06

    CPC分类号： H01L27/0688

    摘要： A stacked semiconductor device has three-dimensional alternate layers of iconductor elements and insulating layers each electrically insulating the adjacent upper and lower layers of semiconductor elements, formed on a single crystal semiconductor substrate. A semiconductor is deposited in openings formed respectively in the insulating layers to form single crystal semiconductor layers each having the same crystal axis as the single crystal semiconductor substrate respectively over the insulating layers, and semiconductor elements are formed respectively in a plurality of layers. The opening formed through the upper insulating layer reaches the lower layer of the semiconductor element immediately below the same upper insulating layer, and is formed at a position spaced apart horizontally from the opening formed through the lower insulating layer immediately below the same upper insulating layer. A semiconductor for forming the upper layer of a semiconductor having the same crystal axis as the lower layer of a semiconductor is deposited in the opening of the upper insulating layer so that satisfactory lateral epitaxial growth will occur over the insulating layer.

    摘要翻译： 叠层半导体器件具有三维交替层的半导体元件和绝缘层，每个绝缘层将形成在单晶半导体衬底上的相邻的半导体元件的上层和下层电绝缘。 分别在绝缘层中形成的开口中沉积半导体，以形成分别在绝缘层上分别与单晶半导体衬底相同的晶轴的单晶半导体层，并分别形成多个半导体元件。 通过上绝缘层形成的开口到达同一上绝缘层正下方的半导体元件的下层，并形成在与通过同一上绝缘层正下方的下绝缘层形成的开口水平间隔开的位置处。 用于形成具有与半导体的下层相同的晶轴的半导体的上层的半导体被沉积在上绝缘层的开口中，使得在绝缘层上将发生令人满意的横向外延生长。

    Multiple layer static random access memory device
    9.
    发明授权
    Multiple layer static random access memory device 失效
    多层静态随机存取存储器件

    公开(公告)号：US5001539A

    公开(公告)日：1991-03-19

    申请号：US337702

    申请日：1989-04-13

    申请人： Yasuo Inoue ,  Tadashi Nishimura

    发明人： Yasuo Inoue ,  Tadashi Nishimura

    IPC分类号： G11C11/412 ,  H01L21/8244 ,  H01L27/00 ,  H01L27/06 ,  H01L27/11

    CPC分类号： H01L27/1104 ,  H01L27/0688 ,  H01L27/1108 ,  Y10S257/903

    摘要： A stacked static random access memory SRAM having a plurality of memory cells is disclosed. Individual memory cell has a portion formed in an upper active element layer in the device structure and a portion formed in a lower active element layer in the device structure separated from the upper layer by an intermediate insulating layer. A word line, a bit line and access transistors are formed in the same upper active element layer, eliminating the need for interconnecting them through the insulating layer. The elimination of the inter-layer connections helps to reduce the number of through-holes required to be made in the insulating layer. This in turn reduces the area to be occupied by the memory cell and leads to a simplified manufacturing process of the SRAM.

    摘要翻译： 公开了一种具有多个存储单元的堆叠静态随机存取存储器SRAM。 单个存储单元具有形成在器件结构中的上有源元件层中的部分，以及通过中间绝缘层与器件结构中的下有源元件层中形成的部分形成在上层中的部分。 在相同的上部有源元件层中形成字线，位线和存取晶体管，消除了通过绝缘层将它们互连的需要。 层间连接的消除有助于减少在绝缘层中制造的通孔的数量。 这又减少了由存储器单元占用的面积，并导致了SRAM的简化制造过程。