公开(公告)号：US4987092A

公开(公告)日：1991-01-22

申请号：US204581

申请日：1988-06-09

申请人： Kiyoteru Kobayashi ,  Tadashi Nishimura ,  Hiroshi Morita ,  Shuji Nakao ,  Hidekazu Oda ,  Yasuo Inoue

发明人： Kiyoteru Kobayashi ,  Tadashi Nishimura ,  Hiroshi Morita ,  Shuji Nakao ,  Hidekazu Oda ,  Yasuo Inoue

IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L21/822 ,  H01L21/8244 ,  H01L27/00 ,  H01L27/092 ,  H01L27/11 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L27/11 ,  H01L21/8221 ,  H01L27/1104 ,  H01L27/1108

摘要： An improved method of manufacturing semiconductor devices having a stacked structure is disclosed. A p-channel semiconductor substrate is prepared, and on the major surface of the substrate, n-channel source and drain regions and a gate electrode are formed to provide a n-channel transistor. Sidewalls are formed of P type single-crystal silicon on the opposite size of the gate electrode of n-channel transistor with an insulating layer interposed between the sidewalls and the gate electrode. A single-crystal layer covers the source, drain and gate electrode of the n-channel transistor and the sidewall structures. A P type impurity present in the sidewalls is diffused into the single-crystal layer.

摘要翻译： 公开了一种制造具有堆叠结构的半导体器件的改进方法。 制备p沟道半导体衬底，并且在衬底的主表面上形成n沟道源极和漏极区域以及栅极电极以提供n沟道晶体管。 侧壁由位于n沟道晶体管的栅电极的相对尺寸上的P型单晶硅形成，其中介于侧壁和栅电极之间的绝缘层。 单晶层覆盖了n沟道晶体管的源极，漏极和栅极以及侧壁结构。 存在于侧壁中的P型杂质扩散到单晶层中。

公开(公告)号：US06351014B2

公开(公告)日：2002-02-26

申请号：US09519598

申请日：2000-03-06

申请人： Yasuo Inoue ,  Tadashi Nishimura ,  Yasuo Yamaguchi ,  Toshiaki Iwamatsu

发明人： Yasuo Inoue ,  Tadashi Nishimura ,  Yasuo Yamaguchi ,  Toshiaki Iwamatsu

IPC分类号： H01L2701

CPC分类号： H01L21/8238 ,  H01L21/84 ,  H01L23/4825 ,  H01L27/0921 ,  H01L27/1203 ,  H01L29/78609 ,  H01L29/78612 ,  H01L29/78615 ,  H01L29/78621 ,  H01L29/78645 ,  H01L29/78654 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to a semiconductor device of the present invention, a field oxide film is formed so as to cover the main surface of an SOI layer and to reach the main surface of a buried oxide film. As a result, a pMOS active region of the SOI and an nMOS active region of the SOI can be electrically isolated completely. Therefore, latchup can be prevented completely. As a result, it is possible to provide a semiconductor device using an SOI substrate which can implement high integration by eliminating reduction of the breakdown voltage between source and drain, which was a problem of a conventional SOI field effect transistor, as well as by efficiently disposing a body contact region, which hampers high integration, and a method of manufacturing the same.

摘要翻译： 根据本发明的半导体器件，形成场致氧化膜以覆盖SOI层的主表面并到达掩埋氧化膜的主表面。 结果，可以完全电隔离SOI的pMOS有源区和SOI的nMOS有源区。 因此，可以完全防止闭锁。 结果，可以提供使用SOI衬底的半导体器件，该SOI衬底可以通过消除源极和漏极之间的击穿电压的降低来实现高集成度，这是常规SOI场效应晶体管的问题，以及有效地 设置妨碍高集成度的身体接触区域及其制造方法。

公开(公告)号：US06319805B1

公开(公告)日：2001-11-20

申请号：US09499733

申请日：2000-02-08

申请人： Toshiaki Iwamatsu ,  Yasuo Inoue ,  Yasuo Yamaguchi ,  Tadashi Nishimura

发明人： Toshiaki Iwamatsu ,  Yasuo Inoue ,  Yasuo Yamaguchi ,  Tadashi Nishimura

IPC分类号： H01L213205

CPC分类号： H01L21/26506 ,  H01L21/26586 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41783 ,  H01L29/458 ,  H01L29/66507 ,  H01L29/66659 ,  H01L29/66772 ,  H01L29/78621

摘要： A semiconductor device in which parasitic resistance of source/drain regions can be reduced than the parasitic resistance of the drain region, and manufacturing method thereof, can be obtained. In the semiconductor device, inactivating ions are implanted only to the source region of the semiconductor layer, so as to damage the crystal near the surface of the semiconductor layer, whereby siliciding reaction is promoted. Therefore, in the source region, a titanium silicide film which is thicker can be formed.

摘要翻译： 可以获得其中源极/漏极区域的寄生电阻可以比漏极区域的寄生电阻降低的半导体器件及其制造方法。 在半导体装置中，仅将钝化离子注入到半导体层的源极区域，以损坏半导体层的表面附近的晶体，从而促进了硅化反应。 因此，在源极区域中，可以形成更厚的硅化钛膜。

公开(公告)号：US5619053A

公开(公告)日：1997-04-08

申请号：US454816

申请日：1995-05-31

申请人： Toshiaki Iwamatsu ,  Yasuo Inoue ,  Tadashi Nishimura

发明人： Toshiaki Iwamatsu ,  Yasuo Inoue ,  Tadashi Nishimura

IPC分类号： H01L27/12 ,  H01L27/01

CPC分类号： H01L27/1203

摘要： Generation of parasitic transistor in active layer edge is prevented, in an NMOS region of a semiconductor layer (21) on an insulating film (20), boron ions are implanted by rotary oblique injection, using a nitride film (23) and a resist (253a) as mask. In the vicinity of a region for separating element by LOCOS method, that is, only in the edge region of the semiconductor layer (21) as the active layer of NMOS transistor, boron ions are implanted by about 3.times.10.sup.13 /cm.sup.2. After LOCOS oxidation, the impurity concentration is heightened to such a level as the boron ions may not be sucked up into the oxide film.

摘要翻译： 在绝缘膜（20）上的半导体层（21）的NMOS区域中，通过旋转斜射注入硼离子，使用氮化物膜（23）和抗蚀剂（...）来防止在有源层边缘中产生寄生晶体管 253a）作为掩模。 在通过LOCOS方法分离元件的区域附近，即仅在作为NMOS晶体管的有源层的半导体层（21）的边缘区域中，硼离子注入约3×10 13 / cm 2。 在LOCOS氧化之后，杂质浓度提高到这样的水平，因为硼离子不能被吸入氧化膜中。

公开(公告)号：US5371381A

公开(公告)日：1994-12-06

申请号：US587500

申请日：1990-09-24

申请人： Kazuyuki Sugahara ,  Tadashi Nishimura ,  Shigeru Kusunoki ,  Yasuo Inoue

发明人： Kazuyuki Sugahara ,  Tadashi Nishimura ,  Shigeru Kusunoki ,  Yasuo Inoue

IPC分类号： H01L21/20 ,  H01L21/268 ,  H01L21/822 ,  H01L29/04 ,  H01L27/04

CPC分类号： H01L21/8221 ,  H01L21/2026 ,  H01L21/268 ,  H01L29/045 ,  Y10S117/904 ,  Y10S148/09 ,  Y10S148/091 ,  Y10S148/093

摘要： Disclosed herein is a process for producing a single crystal layer of a semiconductor device, which comprises the steps of providing an oxide insulator layer separated by an opening part for seeding, on a major surface of a single crystal semiconductor substrate of the cubic system, providing a polycrystalline or amorphous semiconductor layer on the entire surface of the insulator layer inclusive of the opening part, then providing a protective layer comprising at least a reflective or anti-reflection film comprising stripes of a predetermined width, in a predetermined direction relative to the opening part and at a predetermined interval, the protective layer capable of controlling the temperature distributions in the semiconductor layer at the parts corresponding to the stripes or the parts not corresponding to the stripes, thereby completing a base for producing a semiconductor device, thereafter the surface of the base is irradiated with an energy beam through the striped reflective or anti-reflection film to melt the polycrystalline or amorphous semiconductor and scanning the energy beam in a predetermined direction such that the direction of the crystal of the semiconductor re-solidified and converted into a single crystal accords with a {111} plane, to produce the single crystal of the semiconductor device. Also disclosed is a semiconductor device produced by the method, which comprises a single crystal layer having a wide range of a crystal in a predetermined direction relative to the facial orientation of the major surface of the substrate, and has a three-dimensional semiconductor circuit element construction.

摘要翻译： 本发明公开了一种制造半导体器件的单晶层的方法，其包括以下步骤：在立方晶系的单晶半导体衬底的主表面上提供由用于接种的开口部分开的氧化物绝缘体层，提供 在包括开口部分的绝缘体层的整个表面上的多晶或非晶半导体层，然后提供保护层，该保护层至少包括反射膜或防反射膜，该反射膜或防反射膜包含预定宽度的条，相对于开口 部分并且以预定间隔，保护层能够控制对应于条纹的部分或不对应于条纹的部分的半导体层中的温度分布，从而完成用于制造半导体器件的基底，之后， 通过条纹反射照射能量束 e或抗反射膜，以熔化多晶或非晶半导体并沿预定方向扫描能量束，使得半导体晶体的方向重新固化并转换成单晶符合{111}面，至 产生半导体器件的单晶。 还公开了一种通过该方法制造的半导体器件，该半导体器件包括相对于衬底的主表面的面取向在预定方向上具有宽范围的晶体的单晶层，并且具有三维半导体电路元件 施工。

公开(公告)号：US4993835A

公开(公告)日：1991-02-19

申请号：US424979

申请日：1989-10-23

申请人： Yasuo Inoue ,  Tadashi Nishimura

发明人： Yasuo Inoue ,  Tadashi Nishimura

IPC分类号： G01B11/24 ,  G01B11/25

CPC分类号： G01B11/25

摘要： Disclosed is an apparatus for detecting the three-dimensional configuration of an object employing an optical cutting method. A light projector pulse-flashes slit-shaped light and causes the light to scan an object at a predetermined speed. An image sensor having a plurality of pixels is disposed in opposition to the object. An optical system forms on the image sensor an image of an optical cutting line formed on the surface of the object by the light. A difference detector detects the difference between the on- and off- levels of each of pulses of the image detected by the pixels of the sensor. A time calculator calculates the time at which the image has passed each of the pixels, on the basis of the difference detected by the difference detector. A configuration calculator calculates the three-dimensional configuration of the object on the basis of the calculated passage time and the scanning speed of the slit-shaped light. Since the difference between the levels of each pulse of the image is obtained, any optical signals resulting from a factor other than the pertinent pulses, such as influence by the background of the object, or a flash can be excluded, and the configuration can be detected with a high level of precision.

摘要翻译： 公开了一种使用光学切割方法检测物体的三维构造的装置。 光投射器脉冲闪烁狭缝状光，并使光以预定速度扫描物体。 具有多个像素的图像传感器设置成与物体相对。 光学系统在图像传感器上形成通过光形成在物体表面上的光学切割线的图像。 差分检测器检测由传感器的像素检测的图像的每个脉冲的开和关电平之间的差异。 时间计算器基于由差分检测器检测到的差异来计算图像已经通过每个像素的时间。 配置计算器基于所计算的通过时间和狭缝状光的扫描速度来计算物体的三维配置。 由于获得图像的每个脉冲的电平之间的差异，所以可以排除由诸如对象的背景或闪光的相关脉冲之外的因素产生的任何光信号，并且可以将配置 以高精度检测。

公开(公告)号：US4822751A

公开(公告)日：1989-04-18

申请号：US30904

申请日：1987-03-31

申请人： Akira Ishizu ,  Tadashi Nishimura ,  Yasuo Inoue

发明人： Akira Ishizu ,  Tadashi Nishimura ,  Yasuo Inoue

IPC分类号： H01L27/12 ,  H01L21/20 ,  H01L21/205 ,  H01L21/263 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L29/78 ,  H01L29/786 ,  H01L21/268

CPC分类号： H01L21/0262 ,  H01L21/0242 ,  H01L21/02491 ,  H01L21/02532 ,  H01L21/02639 ,  H01L27/1214 ,  H01L29/66757 ,  H01L29/78633 ,  Y10S148/091 ,  Y10S148/093

摘要： A thin film semiconductor device is formed by preparing a substrate, forming a pattern of metal thin film on the substrate, forming an insulating layer on the metal thin film, and forming a pattern of a semiconductor thin film active layer, which is self-aligned to the pattern of the metal thin film, by laser CVD.

摘要翻译： 通过准备基板来形成薄膜半导体器件，在基板上形成金属薄膜图案，在金属薄膜上形成绝缘层，并形成自对准的半导体薄膜有源层的图案 通过激光CVD到金属薄膜的图案。

公开(公告)号：US4787740A

公开(公告)日：1988-11-29

申请号：US11329

申请日：1987-02-05

申请人： Yasuo Inoue ,  Tadashi Nishimura ,  Kazuyuki Sugahara ,  Shigeru Kusunoki

发明人： Yasuo Inoue ,  Tadashi Nishimura ,  Kazuyuki Sugahara ,  Shigeru Kusunoki

IPC分类号： H01L21/66 ,  G01N21/00 ,  G01N21/21 ,  G01N21/65 ,  G01N21/84

CPC分类号： G01N21/65 ,  G01N2021/656 ,  G01N2021/8477 ,  G01N21/21 ,  G01N21/658

摘要： An apparatus for determining crystal orientation comprises: a polarizer for polarizing an incident light beam; a polarization analyzer for selecting light having a selected polarization direction in Raman scattered light; and a synchronizer for enabling synchronous rotations of the polarizer and the polarization analyzer.

摘要翻译： 一种用于确定晶体取向的装置包括：用于偏振入射光束的偏振器; 偏振分析器，用于选择拉曼散射光中具有所选偏振方向的光; 以及用于实现偏振器和偏振分析器的同步旋转的同步器。

公开(公告)号：US4694143A

公开(公告)日：1987-09-15

申请号：US815069

申请日：1985-12-31

申请人： Tadashi Nishimura ,  Kazuyuki Sugahara ,  Shigeru Kusunoki ,  Yasuo Inoue

发明人： Tadashi Nishimura ,  Kazuyuki Sugahara ,  Shigeru Kusunoki ,  Yasuo Inoue

IPC分类号： H01L21/20 ,  C30B13/28 ,  H01L21/26 ,  H05B3/00 ,  H05B3/64 ,  F27B5/14 ,  F27D11/00

CPC分类号： C30B13/28 ,  H05B3/0047

摘要： A zone melting apparatus, in accordance with the present invention for monocrystallizing a semiconductor layer in a layered substance, includes: an upper elongated heater for zone melting of the semiconductor layer, the upper heater being disposed above and parallel to the semiconductor layer; a plurality of lower elongated heaters for heating the whole layered substance, the lower heaters being disposed in a plane below and parallel to the layered substance and the axis of each of the lower heaters being substantially perpendicular to the axis of the upper heater; a plurality of power suppliers for supplying electric power to the lower heaters; one or more temperature sensors for estimating the temperature of the layered substance; and a controller for controlling the power suppliers in response to the output of the temperature sensor(s), the controller making control so that the temperature of the central portion of the layered substance is slightly lower than that of the outer portions thereof.

摘要翻译： 根据本发明的用于使层状物质中的半导体层单晶化的区域熔化装置包括：用于半导体层的区域熔化的上部细长加热器，上部加热器设置在半导体层的上方并平行; 多个下部细长加热器，用于加热整个层状物质，下部加热器设置在层叠物质下方并平行的平面中，并且每个下部加热器的轴线基本上垂直于上部加热器的轴线; 用于向下部加热器供电的多个供电装置; 用于估计分层物质的温度的一个或多个温度传感器; 以及控制器，用于响应于温度传感器的输出来控制供电器，控制器进行控制，使得层状物质的中心部分的温度略低于其外部部分的温度。

公开(公告)号：US5659194A

公开(公告)日：1997-08-19

申请号：US614256

申请日：1996-03-12

申请人： Toshiaki Iwamatsu ,  Yasuo Inoue ,  Yasuo Yamaguchi ,  Tadashi Nishimura

发明人： Toshiaki Iwamatsu ,  Yasuo Inoue ,  Yasuo Yamaguchi ,  Tadashi Nishimura

IPC分类号： H01L21/28 ,  H01L21/265 ,  H01L21/336 ,  H01L21/76 ,  H01L21/84 ,  H01L27/12 ,  H01L29/45 ,  H01L29/78 ,  H01L29/786 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L21/26506 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41783 ,  H01L29/458 ,  H01L29/66507 ,  H01L29/66659 ,  H01L29/66772 ,  H01L21/26586 ,  H01L29/78621

摘要： A semiconductor device in which parasitic resistance of source/drain regions can be reduced than the parasitic resistance of the drain region, and manufacturing method thereof, can be obtained. In the semiconductor device, inactivating ions are implanted only to the source region of the semiconductor layer, so as to damage the crystal near the surface of the semiconductor layer, whereby siliciding reaction is promoted. Therefore, in the source region, a titanium silicide film which is thicker can be formed.

摘要翻译： 可以获得其中源极/漏极区域的寄生电阻可以比漏极区域的寄生电阻降低的半导体器件及其制造方法。 在半导体装置中，仅将钝化离子注入到半导体层的源极区域，以损坏半导体层的表面附近的晶体，从而促进了硅化反应。 因此，在源极区域中，可以形成更厚的硅化钛膜。