公开(公告)号：US06891270B2

公开(公告)日：2005-05-10

申请号：US10245701

申请日：2002-09-18

申请人： Akira Sugawara ,  Nobuhiro Tanaka ,  Ichiro Uehara

发明人： Akira Sugawara ,  Nobuhiro Tanaka ,  Ichiro Uehara

IPC分类号： H01L21/28 ,  H01L21/288 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/77 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/52 ,  H01L27/092 ,  H01L27/12 ,  H01L29/423 ,  H01L29/43 ,  H01L29/45 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01L23/48 ,  H01L23/40

CPC分类号： H01L29/78621 ,  H01L21/2885 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76852 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1292 ,  H01L29/458 ,  H01L2924/0002 ,  H01L2924/00

摘要： A simple technique of forming a low-resistant wire is provided in place of a Damascene method. In a three-layer wire composed of a first layer metal film wire, a second layer metal film wire that has fixed side etching portions, and an insulating film pattern, a low-resistant metal such as copper or silver is deposited in concave regions corresponding to the side etching portions of the second layer metal film wire through electrodeposition by electroplating. The above process is applied to a gate electrode and wire of a semiconductor device to obtain a semiconductor device that has high operation speed.

摘要翻译： 提供了形成低电阻线的简单技术来代替镶嵌法。 在由第一层金属膜线，具有固定侧蚀刻部分的第二层金属膜线以及绝缘膜图案构成的三层布线中，将铜或银等低电阻金属沉积在对应于 通过电镀电沉积到第二层金属膜线的侧蚀刻部分。 将上述工艺应用于半导体器件的栅电极和导线，以获得具有高操作速度的半导体器件。

公开(公告)号：US08324032B2

公开(公告)日：2012-12-04

申请号：US13152492

申请日：2011-06-03

申请人： Hideto Ohnuma ,  Ichiro Uehara

发明人： Hideto Ohnuma ,  Ichiro Uehara

IPC分类号： H01L21/84

CPC分类号： H01L27/1288 ,  H01L21/28114 ,  H01L21/32136 ,  H01L21/32139 ,  H01L27/1214 ,  H01L29/42384 ,  H01L29/66598 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627 ,  H01L2029/7863 ,  Y10S438/949

摘要： Formation of LDD structures and GOLD structures in a semiconductor device is conventionally performed in a self aligning manner with gate electrodes as masks, but there are many cases in which the gate electrodes have two layer structures, and film formation processes and etching processes become complex. Further, in order to perform formation of LDD structures and GOLD structures only by processes such as dry etching, the transistor structures all have the same structure, and it is difficult to form LDD structures, GOLD structures, and single drain structures separately for different circuits. By applying a photolithography process for forming gate electrodes to photomasks or reticles, in which supplemental patterns having a function of reducing, the intensity of light and composed of diffraction grating patterns or translucent films, are established, GOLD structure, LDD structure, and single drain structure transistors can be easily manufactured for different circuits through dry etching and ion injection process steps.

摘要翻译： 通常以半导体器件中的LDD结构和GOLD结构的形式，以栅电极作为掩模进行自对准，但是栅电极具有两层结构的情况很多，成膜工艺和蚀刻工艺变得复杂。 此外，为了仅通过诸如干蚀刻的工艺来形成LDD结构和GOLD结构，晶体管结构都具有相同的结构，并且难以分别形成用于不同电路的LDD结构，GOLD结构和单个漏极结构 。 通过对光栅掩模或掩模版形成栅极电极的光刻工艺，建立了具有降低光的强度并由衍射光栅图案或半透明膜构成的功能的补充图案，GOLD结构，LDD结构和单漏极 通过干蚀刻和离子注入工艺步骤可以容易地为不同的电路制造结构晶体管。

公开(公告)号：US07655328B2

公开(公告)日：2010-02-02

申请号：US11785682

申请日：2007-04-19

申请人： Takao Maeda ,  Yuuichi Makino ,  Hajime Nakano ,  Ichiro Uehara

发明人： Takao Maeda ,  Yuuichi Makino ,  Hajime Nakano ,  Ichiro Uehara

IPC分类号： B32B9/00

CPC分类号： C23C4/08 ,  C23C4/06 ,  Y10T428/31678

摘要： An electrically conductive, plasma-resistant member adapted for exposure to a halogen-based gas plasma atmosphere includes a substrate having formed on at least part of a region thereof to be exposed to the plasma a thermal spray coating composed of yttrium metal or yttrium metal in admixture with yttrium oxide and/or yttrium fluoride so as to confer electrical conductivity. Because the member is conductive and has an improved erosion resistance to halogen-based corrosive gases or plasmas thereof, particle contamination due to plasma etching when used in semiconductor manufacturing equipment or flat panel display manufacturing equipment can be suppressed.

摘要翻译： 适于暴露于基于卤素的气体等离子体气氛的导电等离子体构件包括在其至少部分区域上形成以暴露于等离子体的基底，其由钇金属或钇金属组成的热喷涂 与氧化钇和/或氟化钇混合以赋予导电性。 由于该部件是导电的并且具有改进的对卤素腐蚀性气体或其等离子体的耐腐蚀性，因此可以抑制当用于半导体制造设备或平板显示器制造设备时由于等离子体蚀刻引起的颗粒污染。

公开(公告)号：US07514868B2

公开(公告)日：2009-04-07

申请号：US10827709

申请日：2004-04-20

申请人： Shunpei Yamazaki ,  Hideomi Suzawa ,  Ichiro Uehara

发明人： Shunpei Yamazaki ,  Hideomi Suzawa ,  Ichiro Uehara

IPC分类号： H05B33/00

CPC分类号： H01L27/323 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/3246 ,  Y10S428/917

摘要： In an EL element having an anode, an insulating film (bump) formed on the anode, and an EL film and a cathode formed on the insulating film, each of a bottom end portion and a top end portion of the insulating film is formed so as to have a curved surface. The taper angle of a central portion of the insulating film is set within the range from 35° to 70°, thereby preventing the gradient of the film forming surface on which the EL film and the cathode are to be formed from being abruptly changed. On the thus-formed film forming surface, the EL film and the cathode can be formed so as to be uniform in thickness, so that occurrence of discontinuity in each of EL film and the cathode is prevented.

公开(公告)号：US20080182209A1

公开(公告)日：2008-07-31

申请号：US12016244

申请日：2008-01-18

申请人： Masaharu Nagai ,  Ichiro Uehara

发明人： Masaharu Nagai ,  Ichiro Uehara

IPC分类号： G03F7/26

CPC分类号： H01L27/1288 ,  G03F7/40 ,  H01L21/0273 ,  H01L21/32136 ,  H01L21/32139 ,  H01L27/1214 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78675

摘要： In a resist pattern forming method in which bake processing is performed at a temperature not lower than a glass transition temperature in order to obtain the desired sidewall angle, resist removable is difficult. Accordingly, in the resist pattern forming method of performing bake processing at a temperature not lower than a glass transition temperature, a process margin for resist removability cannot be ensured, so that there is the problem that it is impossible to compatibly realize both the formation of a resist pattern having the desired sidewall angle and the resist removability of the resist pattern. The invention aims to solve the problem. A resist pattern including a diazonaphthoquinone (DNQ)-novolac resin type of positive resist is formed, and the resist pattern is irradiated with light within the range of photosensitive wavelengths of a DNQ photosensitizer to perform bake processing on the resist pattern at a temperature not lower than the glass transition temperature of the resist pattern.

摘要翻译： 在为了获得期望的侧壁角度而在不低于玻璃化转变温度的温度进行烘烤处理的抗蚀剂图案形成方法中，难以除去抗蚀剂。 因此，在不低于玻璃化转变温度的温度进行烘烤处理的抗蚀剂图案形成方法中，不能确保抗蚀剂除去性的工艺余量，所以存在不能兼容地实现 抗蚀剂图案具有期望的侧壁角度和抗蚀剂图案的抗蚀剂可除去性。 本发明旨在解决问题。 形成包含重氮萘醌（DNQ） - 新型异氰酸酯树脂型正性抗蚀剂的抗蚀剂图案，用DNQ光敏剂的光敏波长范围内的光照射抗蚀剂图案，以在不低于的温度对抗蚀剂图案进行烘烤处理 比抗蚀剂图案的玻璃化转变温度高。

公开(公告)号：US20070218604A1

公开(公告)日：2007-09-20

申请号：US11754484

申请日：2007-05-29

申请人： Hideto Ohnuma ,  Ichiro Uehara

发明人： Hideto Ohnuma ,  Ichiro Uehara

IPC分类号： H01L21/84

CPC分类号： H01L27/1288 ,  H01L21/28114 ,  H01L21/32136 ,  H01L21/32139 ,  H01L27/1214 ,  H01L29/42384 ,  H01L29/66598 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627 ,  H01L2029/7863 ,  Y10S438/949

摘要： Formation of LDD structures and GOLD structures in a semiconductor device is conventionally performed in a self aligning manner with gate electrodes as masks, but there are many cases in which the gate electrodes have two layer structures, and film formation processes and etching processes become complex. Further, in order to perform formation of LDD structures and GOLD structures only by processes such as dry etching, the transistor structures all have the same structure, and it is difficult to form LDD structures, GOLD structures, and single drain structures separately for different circuits. By applying a photolithography process for forming gate electrodes to photomasks or reticles, in which supplemental patterns having a function of reducing the intensity of light and composed of diffraction grating patterns or translucent films, are established, GOLD structure, LDD structure, and single drain structure transistors can be easily manufactured for different circuits through dry etching and ion injection process steps.

摘要翻译： 通常以半导体器件中的LDD结构和GOLD结构的形式，以栅电极作为掩模进行自对准，但是栅电极具有两层结构的情况很多，成膜工艺和蚀刻工艺变得复杂。 此外，为了仅通过诸如干蚀刻的工艺来形成LDD结构和GOLD结构，晶体管结构都具有相同的结构，并且难以分别形成用于不同电路的LDD结构，GOLD结构和单个漏极结构 。 通过应用用于形成栅电极的光刻工艺来形成光掩模或掩模版，其中具有降低光强度并且由衍射光栅图案或半透明膜构成的功能的补充图案，GOLD结构，LDD结构和单漏极结构 通过干蚀刻和离子注入工艺步骤可以容易地为不同的电路制造晶体管。

公开(公告)号：US20060014335A1

公开(公告)日：2006-01-19

申请号：US11224047

申请日：2005-09-13

申请人： Hideto Ohnuma ,  Ichiro Uehara

发明人： Hideto Ohnuma ,  Ichiro Uehara

IPC分类号： H01L21/84

CPC分类号： H01L27/1288 ,  H01L21/28114 ,  H01L21/32136 ,  H01L21/32139 ,  H01L27/1214 ,  H01L29/42384 ,  H01L29/66598 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627 ,  H01L2029/7863 ,  Y10S438/949

摘要： Formation of LDD structures and GOLD structures in a semiconductor device is conventionally performed in a self aligning manner with gate electrodes as masks, but there are many cases in which the gate electrodes have two layer structures, and film formation processes and etching processes become complex. Further, in order to perform formation of LDD structures and GOLD structures only by processes such as dry etching, the transistor structures all have the same structure, and it is difficult to form LDD structures, GOLD structures, and single drain structures separately for different circuits. By applying a photolithography process for forming gate electrodes to photomasks or reticles, in which supplemental patterns having a function of reducing the intensity of light and composed of diffraction grating patterns or translucent films, are established, GOLD structure, LDD structure, and single drain structure transistors can be easily manufactured for different circuits through dry etching and ion injection process steps.

公开(公告)号：US07955912B2

公开(公告)日：2011-06-07

申请号：US12823175

申请日：2010-06-25

申请人： Hideto Ohnuma ,  Ichiro Uehara

发明人： Hideto Ohnuma ,  Ichiro Uehara

IPC分类号： H01L21/84

CPC分类号： H01L27/1288 ,  H01L21/28114 ,  H01L21/32136 ,  H01L21/32139 ,  H01L27/1214 ,  H01L29/42384 ,  H01L29/66598 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627 ,  H01L2029/7863 ,  Y10S438/949

摘要： Formation of LDD structures and GOLD structures in a semiconductor device is conventionally performed in a self aligning manner with gate electrodes as masks, but there are many cases in which the gate electrodes have two layer structures, and film formation processes and etching processes become complex. Further, in order to perform formation of LDD structures and GOLD structures only by processes such as dry etching, the transistor structures all have the same structure, and it is difficult to form LDD structures, GOLD structures, and single drain structures separately for different circuits. By applying a photolithography process for forming gate electrodes to photomasks or reticles, in which supplemental patterns having a function of reducing the intensity of light and composed of diffraction grating patterns or translucent films, are established, GOLD structure, LDD structure, and single drain structure transistors can be easily manufactured for different circuits through dry etching and ion injection process steps.

摘要翻译： 通常以半导体器件中的LDD结构和GOLD结构的形式，以栅电极作为掩模进行自对准，但是栅电极具有两层结构的情况很多，成膜工艺和蚀刻工艺变得复杂。 此外，为了仅通过诸如干蚀刻的工艺来形成LDD结构和GOLD结构，晶体管结构都具有相同的结构，并且难以分别形成用于不同电路的LDD结构，GOLD结构和单个漏极结构 。 通过应用用于形成栅电极的光刻工艺来形成光掩模或掩模版，其中具有降低光强度并且由衍射光栅图案或半透明膜构成的功能的补充图案，GOLD结构，LDD结构和单漏极结构 通过干蚀刻和离子注入工艺步骤可以容易地为不同的电路制造晶体管。

公开(公告)号：US20080119024A1

公开(公告)日：2008-05-22

申请号：US11969247

申请日：2008-01-04

申请人： Hideto Ohnuma ,  Ichiro Uehara

发明人： Hideto Ohnuma ,  Ichiro Uehara

IPC分类号： H01L21/04

CPC分类号： H01L27/1288 ,  H01L21/28114 ,  H01L21/32136 ,  H01L21/32139 ,  H01L27/1214 ,  H01L29/42384 ,  H01L29/66598 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627 ,  H01L2029/7863 ,  Y10S438/949

摘要： Formation of LDD structures and GOLD structures in a semiconductor device is conventionally performed in a self aligning manner with gate electrodes as masks, but there are many cases in which the gate electrodes have two layer structures, and film formation processes and etching processes become complex. Further, in order to perform formation of LDD structures and GOLD structures only by processes such as dry etching, the transistor structures all have the same structure, and it is difficult to form LDD structures, GOLD structures, and single drain structures separately for different circuits. By applying a photolithography process for forming gate electrodes to photomasks or reticles, in which supplemental patterns having a function of reducing the intensity of light and composed of diffraction grating patterns or translucent films, are established, GOLD structure, LDD structure, and single drain structure transistors can be easily manufactured for different circuits through dry etching and ion injection process steps.

摘要翻译： 通常以半导体器件中的LDD结构和GOLD结构的形式，以栅电极作为掩模进行自对准，但是栅电极具有两层结构的情况很多，成膜工艺和蚀刻工艺变得复杂。 此外，为了仅通过诸如干蚀刻的工艺来形成LDD结构和GOLD结构，晶体管结构都具有相同的结构，并且难以分别形成用于不同电路的LDD结构，GOLD结构和单个漏极结构 。 通过应用用于形成栅电极的光刻工艺来形成光掩模或掩模版，其中具有降低光强度并且由衍射光栅图案或半透明膜构成的功能的补充图案，GOLD结构，LDD结构和单漏极结构 通过干蚀刻和离子注入工艺步骤可以容易地为不同的电路制造晶体管。

公开(公告)号：US20070248832A1

公开(公告)日：2007-10-25

申请号：US11785682

申请日：2007-04-19

申请人： Takao Maeda ,  Yuuichi Makino ,  Hajime Nakano ,  Ichiro Uehara

发明人： Takao Maeda ,  Yuuichi Makino ,  Hajime Nakano ,  Ichiro Uehara

IPC分类号： B32B15/04

CPC分类号： C23C4/08 ,  C23C4/06 ,  Y10T428/31678

摘要： An electrically conductive, plasma-resistant member adapted for exposure to a halogen-based gas plasma atmosphere includes a substrate having formed on at least part of a region thereof to be exposed to the plasma a thermal spray coating composed of yttrium metal or yttrium metal in admixture with yttrium oxide and/or yttrium fluoride so as to confer electrical conductivity. Because the member is conductive and has an improved erosion resistance to halogen-based corrosive gases or plasmas thereof, particle contamination due to plasma etching when used in semiconductor manufacturing equipment or flat panel display manufacturing equipment can be suppressed.

摘要翻译： 适于暴露于基于卤素的气体等离子体气氛的导电等离子体构件包括在其至少部分区域上形成以暴露于等离子体的基底，其由钇金属或钇金属组成的热喷涂 与氧化钇和/或氟化钇混合以赋予导电性。 由于该部件是导电的并且具有改进的对卤素腐蚀性气体或其等离子体的耐腐蚀性，因此可以抑制当用于半导体制造设备或平板显示器制造设备时由于等离子体蚀刻引起的颗粒污染。