公开(公告)号：US20100120537A1

公开(公告)日：2010-05-13

申请号：US12593043

申请日：2008-02-29

申请人： Akira Yamaoka ,  Takahide Murakami

发明人： Akira Yamaoka ,  Takahide Murakami

IPC分类号： A63F9/24 ,  A63F13/00

CPC分类号： A63F13/215 ,  A63B23/18 ,  A63B23/185 ,  A63B24/0087 ,  A63B71/0622 ,  A63B71/0686 ,  A63B2024/0012 ,  A63B2024/0078 ,  A63B2024/0096 ,  A63B2071/068 ,  A63B2220/17 ,  A63B2220/808 ,  A63B2230/40 ,  A63B2230/42 ,  A63F13/10 ,  A63F13/424 ,  A63F13/44 ,  A63F13/46 ,  A63F2300/1081 ,  A63F2300/6072 ,  A63F2300/638 ,  A63F2300/8094

摘要： In a game device (200), a storage unit (201) stores information indicating a position, a posture and an orientation of a character object to serve as a model, breathing instruction information specifying a time period in which a player should exhale, and a position of a detecting unit (203) detecting a sound production of the player. A deriving unit (204) derives a time period in which the player is taking a breath from a sound production detected by the detecting unit (203). A scoring unit (205) compares the breathing instruction information stored in the storage unit (201) with a time period derived by the deriving unit (204), and gives scores the breathing of the player based on a degree of agreement therebetween. An output unit (206) outputs a result of scoring by the scoring unit (205). A display unit (202) displays an image containing the scoring result and the character object.

摘要翻译： 在游戏装置（200）中，存储单元（201）存储指示作为模型的角色对象的位置，姿势和姿势的信息，指定玩家应该呼出的时间段的呼吸指示信息，以及 检测单元（203）的位置，用于检测播放器的声音产生。 导出单元（204）从由检测单元（203）检测到的声音产生导出玩家正在呼吸的时间段。 评分单元（205）将存储在存储单元（201）中的呼吸指令信息与由导出单元（204）导出的时间段进行比较，并且基于它们之间的一致程度给出玩家呼吸的得分。 输出单元（206）输出得分单元（205）的得分结果。 显示单元（202）显示包含评分结果和字符对象的图像。

公开(公告)号：US5214759A

公开(公告)日：1993-05-25

申请号：US526718

申请日：1990-05-22

申请人： Akira Yamaoka ,  Kenichi Wada

发明人： Akira Yamaoka ,  Kenichi Wada

IPC分类号： G06F15/16 ,  G06F15/167 ,  G06F15/177

CPC分类号： G06F15/167

摘要： In a memory device shared among processors, a communication buffer having a size requested by the processing program of the origin of sending is dynamically secured. After the communication buffer has been secured, the send program writes a message to be conveyed to the receive program into the above described communication buffer and asks the send OS to perform sending. The send OS sends a communication ID having "1" set in the bit position corresponding to the receive program. On the basis of the above described bit position, the receive OS specifies a receive program and informs the receive program of that fact. The receive program reads a message from the communication buffer. Communication between the send program and the receive program is thus realized. A send instruction and a receive instruction respectively for exclusive use of sending and reading out a communication ID are prepared beforehand.

摘要翻译： 在处理器之间共享的存储器装置中，动态地确保具有处理程序所请求的发送原点的通信缓冲器。 在通信缓冲器已被保护之后，发送程序将要传送到接收程序的消息写入上述通信缓冲器，并请求发送OS执行发送。 发送OS在与接收程序相对应的比特位置中发送具有“1”的通信ID。 基于上述位位置，接收OS指定接收程序并通知接收程序该事实。 接收程序从通信缓冲区读取消息。 因此实现了发送程序和接收程序之间的通信。 预先准备分别发送和读出通信ID的发送指令和接收指令。

公开(公告)号：US4758949A

公开(公告)日：1988-07-19

申请号：US928055

申请日：1986-11-07

申请人： Kenichi Wada ,  Kazunori Kuriyama ,  Akira Yamaoka

发明人： Kenichi Wada ,  Kazunori Kuriyama ,  Akira Yamaoka

IPC分类号： G06F9/38

CPC分类号： G06F9/3873 ,  G06F9/3802 ,  G06F9/3836

摘要： An information processing apparatus having a buffer register for pre-fetching a plurality of instructions and executing one instruction after another by reading them from the buffer registers, is provided with a first instruction decode start determination unit for register type instructions and a second instruction decode start determination unit for non-register type instructions, provided separately from the first unit, whereby 0.5 cycle after a register type instruction starts being decoded, or 1 cycle after a non-register type instruction starts being decoded, the next instruction starts to be decoded. By decoding a register type instruction at high speed, it becomes possible to execute a branch instruction at high speed.

摘要翻译： 具有用于预取多个指令并且通过从缓冲寄存器读取它们来执行一个指令的缓冲寄存器的信息处理装置设置有用于寄存器类型指令的第一指令解码开始确定单元和第二指令解码开始 与第一单元分开设置的非寄存器类型指令的确定单元，其中在寄存器类型指令开始被解码之后的0.5个周期，或者在非寄存器类型指令开始被解码之后的1个周期，下一个指令开始被解码。 通过高速解码寄存器类型指令，可以高速执行分支指令。

公开(公告)号：US5201040A

公开(公告)日：1993-04-06

申请号：US209073

申请日：1988-06-20

申请人： Kenichi Wada ,  Akira Yamaoka

发明人： Kenichi Wada ,  Akira Yamaoka

IPC分类号： G06F15/17

CPC分类号： G06F15/17

摘要： A data processing system which has a plurality of sets of sub-systems, with each set including: a plurality of processors; a main storage; and a controller for controlling the transfer between at least each of the processors and the main storage. A shared storage apparatus is shared between the sub-systems to store exclusive control information, information on the processor-to-processor communications and an instruction to be transferred between the main storages and the shared storage apparatus when the information is accessed by each sub-system. The instruction designates a main storage address, a transfer data length and specified information on accessing the location of the shared storage apparatus and is decoded by the processors to that the main storage address is transferred to the main storage, whereas the specified information such as a data identifier and a relative address is transferred to the shared storage apparatus.

摘要翻译： 一种具有多组子系统的数据处理系统，每组包括：多个处理器; 主要存储; 以及用于控制至少每个处理器和主存储器之间的传送的控制器。 在每个子系统访问信息时，在子系统之间共享共享存储装置以存储专用控制信息，关于处理器到处理器通信的信息和要在主存储器和共享存储装置之间传送的指令， 系统。 该指令指定主存储地址，传输数据长度和关于访问共享存储设备的位置的指定信息，并且被处理器解码为主存储地址被传送到主存储器，而指定的信息例如 数据标识符和相对地址被传送到共享存储装置。

公开(公告)号：US4954947A

公开(公告)日：1990-09-04

申请号：US336741

申请日：1989-03-21

申请人： Kazunori Kuriyama ,  Kenichi Wada ,  Akira Yamaoka

发明人： Kazunori Kuriyama ,  Kenichi Wada ,  Akira Yamaoka

IPC分类号： G06F9/38

CPC分类号： G06F9/3824

摘要： An instruction processor effecting operations for register operands and for processing branch instructions to perform address calculations for branch destination instructions, comprising general-purpose registers storing data including results of operations of said instruction processor, address adders calculating the address of branch destination instructions by using data read out from the general-purpose register and an ALU performing arithmetical or logical operations on the data read out from the general-purpose register in the decode cycle of the instructions. The result of the arithmetical or logical operation is inputted into the address adder but not from the general-purpose register, in the case where the result of the arithmetical or logical operation is utilized for address calculation in the execution of a succeeding instruction.

摘要翻译： 指令处理器对寄存器操作数进行操作并处理分支指令以执行分支目的地指令的地址计算，包括通用寄存器，其存储包括所述指令处理器的操作结果的数据，地址加法器通过使用数据计算分支目的地指令的地址 从通用寄存器读出，以及ALU对指令的解码周期中从通用寄存器读出的数据执行算术或逻辑运算。 在执行后续指令时，算术运算或逻辑运算的结果被用于地址计算的情况下，将算术或逻辑运算的结果输入到地址加法器而不是通用寄存器。

公开(公告)号：US4366362A

公开(公告)日：1982-12-28

申请号：US231141

申请日：1981-02-03

申请人： Ichiro Ohta ,  Akio Tejima ,  Masayuki Watando ,  Akira Yamaoka ,  Kouzi Ishiwata ,  Minoru Yamada

发明人： Ichiro Ohta ,  Akio Tejima ,  Masayuki Watando ,  Akira Yamaoka ,  Kouzi Ishiwata ,  Minoru Yamada

IPC分类号： B23K9/16 ,  B23K9/09 ,  B23K9/167

CPC分类号： B23K9/091 ,  B23K9/167

摘要： In a TIG welding process with controlled welding current pulses, DC current pulses with the frequency set at from tens to hundreds Hz (most preferably from 30 to 300 Hz) are fed to an electrode and current pulses are also fed to a filler wire so that an arc is caused to swing, whereby a large pool of molten metal can be maintained in a positive and stable manner due to the high arc pressure obtained when the welding current pulses at from tens to hundreds Hz is used.

摘要翻译： 在具有受控焊接电流脉冲的TIG焊接工艺中，将频率设置为几十到几百赫兹（最优选30至300Hz）的直流电流脉冲馈送到电极，并且电流脉冲也被馈送到填充线，使得 使电弧摆动，由于当使用几十到数百赫兹的焊接电流脉冲时获得的高电弧压力，可以以正和稳定的方式保持大量的熔融金属。

公开(公告)号：US5490259A

公开(公告)日：1996-02-06

申请号：US93969

申请日：1993-07-21

申请人： Tohru Hiraoka ,  Hiromichi Kainoh ,  Akira Yamaoka

发明人： Tohru Hiraoka ,  Hiromichi Kainoh ,  Akira Yamaoka

IPC分类号： G06F12/08 ,  G06F12/10

CPC分类号： G06F12/1027

摘要： Under such a condition between outputs of AND circuits for outputting All "0" when one of zero detecting circuits of two register identifiers within an instruction register detects "0", instead of a content of a general-purpose register designated by these identifiers, and also a carry derived from a page offset corresponding to an intermediate result of an address adder, when a page address portion of a logical address is known before this logical address is defined, selecting circuits are controlled, and then the address controller is bypassed to retrieve a translation look-aside buffer, thereby defining a real address. In case that the page address portion of the logical address register is identical to the page address portion of the base register, the translation look-aside buffer is previously retrieved in accordance with either the content of the index register, or the content of the base register so that the real address can be defined.

摘要翻译： 在指令寄存器内的两个寄存器标识符的零检测电路之一检测到“0”时，用于输出全“0”的AND电路的输出之间的这种条件，而不是由这些标识符指定的通用寄存器的内容，以及 也是从与地址加法器的中间结果相对应的页偏移得到的进位，当在定义该逻辑地址之前逻辑地址的页地址部分已知时，选择电路被控制，然后旁路地址控制器以检索 翻译后备缓冲区，从而定义一个实际地址。 在逻辑地址寄存器的页地址部分与基址寄存器的页地址部分相同的情况下，根据索引寄存器的内容或基址的内容预先检索翻译后备缓冲器 注册，以便可以定义实际地址。

公开(公告)号：US4924377A

公开(公告)日：1990-05-08

申请号：US687161

申请日：1984-12-28

申请人： Kazunori Kuriyama ,  Kenichi Wada ,  Akira Yamaoka

发明人： Kazunori Kuriyama ,  Kenichi Wada ,  Akira Yamaoka

IPC分类号： G06F9/34 ,  G06F9/345 ,  G06F9/355 ,  G06F9/38

CPC分类号： G06F9/355 ,  G06F9/345 ,  G06F9/383

摘要： Address calculation adders and a buffer storages are each independently provided for each operand of an instruction requiring two or more operands. In the translation instruction processing, the address calculations and operand fetch operations on the first and second operands are substantially asynchronously conducted. Consequently, the overhead that takes place one every n second operand fetch operations can be removed by independently and asynchronously performing the address calculations and operand fetch operations by use of a plurality of address adders. Moreover, the circuit for separating and obtaining a byte from the operand buffer can be dispensed with by adopting an operation procedure in which a byte of the first operand is fetched and is stored in temporary store means that supplies the address adder the data stored therein.

摘要翻译： 对于需要两个或多个操作数的指令的每个操作数，地址计算加法器和缓冲存储器都是独立提供的。 在转换指令处理中，对第一和第二操作数的地址计算和操作数获取操作基本上异步进行。 因此，可以通过使用多个地址加法器独立地和异步地执行地址计算和操作数获取操作来移除每n个第二操作数获取操作发生一次的开销。 此外，可以通过采用其中获取第一操作数的字节的操作过程来存储用于从操作数缓冲器分离和获得字节的电路，并将其存储在向地址加法器提供其中存储的数据的临时存储装置中。

公开(公告)号：US4739470A

公开(公告)日：1988-04-19

申请号：US489349

申请日：1983-04-28

申请人： Kenichi Wada ,  Yooichi Shintani ,  Tsuguo Shimizu ,  Akira Yamaoka

发明人： Kenichi Wada ,  Yooichi Shintani ,  Tsuguo Shimizu ,  Akira Yamaoka

IPC分类号： G06F9/38

CPC分类号： G06F9/3889 ,  G06F9/383

摘要： A data processing system for executing an instruction in a plurality of stages in a pipeline mode comprises a main operation unit capable of executing all instructions to be executed in the data processing system, a pre-operation unit capable of executing instructions which occurs at a high frequency and can be executed with a small number of circuit components, general purpose registers for storing operation results of the instructions, and a control unit for controlling the writing of the operation results by the main operation unit and the pre-operation unit into the general purpose registers.

摘要翻译： 一种用于在流水线模式中执行多级指令的数据处理系统，包括能够执行在数据处理系统中执行的所有指令的主操作单元，能够执行高位指令的预操作单元 并且可以用少量的电路部件执行，用于存储指令的操作结果的通用寄存器，以及用于控制主操作单元和预操作单元的操作结果写入一般的控制单元 目的寄存器。

公开(公告)号：US4608671A

公开(公告)日：1986-08-26

申请号：US490518

申请日：1983-05-02

申请人： Tsuguo Shimizu ,  Kenichi Wada ,  Yooichi Shintani ,  Akira Yamaoka

发明人： Tsuguo Shimizu ,  Kenichi Wada ,  Yooichi Shintani ,  Akira Yamaoka

IPC分类号： G06F12/08 ,  G06F12/12 ,  G11C8/00

CPC分类号： G06F12/128

摘要： In a buffer storage device where swapping of data is employed, plural candidates for replacement of data in a buffer are determined in response to any access to the buffer storage, and, when the replacement is required, one of the candidates is selected so that processing time for replacement can be minimum.

摘要翻译： 在采用交换数据的缓冲存储装置中，响应于对缓冲存储器的任何访问来确定用于替换缓冲器中的数据的多个候选，并且当需要更换时，选择候选中的一个，使得处理 更换时间可以是最少的。