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    Using metal/metal nitride bilayers as gate electrodes in self-aligned aggressively scaled CMOS devices
    4.
    发明申请
    Using metal/metal nitride bilayers as gate electrodes in self-aligned aggressively scaled CMOS devices 有权
    使用金属/金属氮化物双层作为自对准积极缩放的CMOS器件中的栅电极

    公开(公告)号：US20060237796A1

    公开(公告)日：2006-10-26

    申请号：US11111592

    申请日：2005-04-21

    申请人： Eduard Cartier ,  Matthew Copel ,  Bruce Doris ,  Rajarao Jammy ,  Young-Hee Kim ,  Barry Linder ,  Vijay Narayanan ,  Vamsi Paruchuri ,  Keith Wong

    发明人： Eduard Cartier ,  Matthew Copel ,  Bruce Doris ,  Rajarao Jammy ,  Young-Hee Kim ,  Barry Linder ,  Vijay Narayanan ,  Vamsi Paruchuri ,  Keith Wong

    IPC分类号： H01L29/76

    CPC分类号： H01L21/823842

    摘要： The present invention is directed to CMOS structures that include at least one nMOS device located on one region of a semiconductor substrate; and at least one pMOS device located on another region of the semiconductor substrate. In accordance with the present invention, the at least one nMOS device includes a gate stack comprising a gate dielectric, a low workfunction elemental metal having a worfunction of less than 4.2 eV, an in-situ metallic capping layer, and a polysilicon encapsulation layer and the at least one pMOS includes a gate stack comprising a gate dielectric, a high workfunction elemental metal having a workfunction of greater than 4.9 eV, a metallic capping layer, and a polysilicon encapsulation layer. The present invention also provides methods of fabricating such a CMOS structure.

    摘要翻译： 本发明涉及包括位于半导体衬底的一个区域上的至少一个nMOS器件的CMOS结构; 以及位于半导体衬底的另一区域上的至少一个pMOS器件。 根据本发明，至少一个nMOS器件包括栅堆叠，其包括栅极电介质，功能小于4.2eV的低功函数元素金属，原位金属覆盖层和多晶硅封装层，以及 所述至少一个pMOS包括包括栅极电介质的栅极堆叠，具有大于4.9eV的功函数的高功函数元素金属，金属覆盖层和多晶硅封装层。 本发明还提供了制造这种CMOS结构的方法。

    Metal gate CMOS with at least a single gate metal and dual gate dielectrics
    5.
    发明申请
    Metal gate CMOS with at least a single gate metal and dual gate dielectrics 有权
    具有至少一个栅极金属和双栅极电介质的金属栅极CMOS

    公开(公告)号：US20070148838A1

    公开(公告)日：2007-06-28

    申请号：US11320330

    申请日：2005-12-28

    申请人： Bruce Doris ,  Young-Hee Kim ,  Barry Linder ,  Vijay Narayanan ,  Vamsi Paruchuri

    发明人： Bruce Doris ,  Young-Hee Kim ,  Barry Linder ,  Vijay Narayanan ,  Vamsi Paruchuri

    IPC分类号： H01L21/8234

    CPC分类号： H01L21/823857 ,  H01L21/823878 ,  H01L21/84

    摘要： A complementary metal oxide semiconductor (CMOS) structure including at least one nFET and at least one pFET located on a surface of a semiconductor substrate is provided. In accordance with the present invention, the nFET and the pFET both include at least a single gate metal and the nFET gate stack is engineered to have a gate dielectric stack having no net negative charge and the pFET gate stack is engineered to have a gate dielectric stack having no net positive charge. In particularly, the present invention provides a CMOS structure in which the nFET gate stack is engineered to include a band edge workfunction and the pFET gate stack is engineered to have a ¼gap workfunction. In one embodiment of the present invention, the first gate dielectric stack includes a first high k dielectric and an alkaline earth metal-containing layer or a rare earth metal-containing layer, while the second high k gate dielectric stack comprises a second high k dielectric.

    摘要翻译： 提供了包括位于半导体衬底的表面上的至少一个nFET和至少一个pFET的互补金属氧化物半导体（CMOS）结构。 根据本发明，nFET和pFET都包括至少一个栅极金属，并且nFET栅极堆叠被设计成具有不具有净负电荷的栅极电介质堆叠，并且pFET栅极堆叠被工程化以具有栅极电介质 堆没有净正电荷。 特别地，本发明提供了一种CMOS结构，其中nFET栅极堆叠被设计成包括带边缘功函数，并且pFET栅极堆叠被设计为具有1/4间隙功函数。 在本发明的一个实施例中，第一栅极电介质堆叠包括第一高k电介质和含碱土金属的层或含稀土金属的层，而第二高k栅介质叠层包括第二高k电介质 。

    Introduction of metal impurity to change workfunction of conductive electrodes
    6.
    发明申请
    Introduction of metal impurity to change workfunction of conductive electrodes 有权
    引入金属杂质来改变导电电极的功能

    公开(公告)号：US20070173008A1

    公开(公告)日：2007-07-26

    申请号：US11336727

    申请日：2006-01-20

    申请人： Michael Chudzik ,  Bruce Doris ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri ,  Yun Wang ,  Keith Wong

    发明人： Michael Chudzik ,  Bruce Doris ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri ,  Yun Wang ,  Keith Wong

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/517 ,  H01L21/28088 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Semiconductor structures, such as, for example, field effect transistors (FETs) and/or metal-oxide-semiconductor capacitor (MOSCAPs), are provided in which the workfunction of a conductive electrode stack is changed by introducing metal impurities into a metal-containing material layer which, together with a conductive electrode, is present in the electrode stack. The choice of metal impurities depends on whether the electrode is to have an n-type workfunction or a p-type workfunction. The present invention also provides a method of fabricating such semiconductor structures. The introduction of metal impurities can be achieved by codeposition of a layer containing both a metal-containing material and workfunction altering metal impurities, forming a stack in which a layer of metal impurities is present between layers of a metal-containing material, or by forming a material layer including the metal impurities above and/or below a metal-containing material and then heating the structure so that the metal impurities are introduced into the metal-containing material.

    摘要翻译： 提供半导体结构，例如场效应晶体管（FET）和/或金属氧化物半导体电容器（MOSCAP），其中通过将金属杂质引入到含金属的物质中来改变导电电极堆叠的功函数 材料层与导电电极一起存在于电极堆叠中。 金属杂质的选择取决于电极是否具有n型功函数或p型功函数。 本发明还提供一种制造这种半导体结构的方法。 金属杂质的引入可以通过共沉积含有金属的材料和改变金属杂质的功函数的层来形成，形成其中金属杂质层存在于含金属材料的层之间的叠层，或通过形成 包括在含金属材料上方和/或下面的金属杂质的材料层，然后加热该结构，使得金属杂质被引入到含金属的材料中。

    Metal gate high-K devices having a layer comprised of amorphous silicon
    8.
    发明授权
    Metal gate high-K devices having a layer comprised of amorphous silicon 有权
    具有由非晶硅组成的层的金属栅极高K器件

    公开(公告)号：US07847356B2

    公开(公告)日：2010-12-07

    申请号：US12542855

    申请日：2009-08-18

    申请人： Tze-Chiang Chen ,  Bruce B. Doris ,  Vijay Narayanan ,  Vamsi Paruchuri

    发明人： Tze-Chiang Chen ,  Bruce B. Doris ,  Vijay Narayanan ,  Vamsi Paruchuri

    IPC分类号： H01L27/088 ,  H01L27/092 ,  H01L29/78

    CPC分类号： H01L21/823842 ,  H01L21/28079 ,  H01L21/823857 ,  H01L21/823878 ,  H01L29/517

    摘要： Disclosed is a method to fabricate a semiconductor device, and a device fabricated in accordance with the method. The method includes providing a substrate comprised of silicon; performing a shallow trench isolation process to delineate nFET and pFET active areas and, within each active area, forming a gate structure over a surface of the substrate, the gate structure comprising in order from the surface of the substrate, a layer of high dielectric constant oxide, a layer comprised of a metal, a layer comprised of amorphous silicon, and a layer comprised of polycrystalline silicon. The layer comprised of amorphous silicon is provided to substantially prevent regrowth of the high dielectric constant oxide layer in a vertical direction during at least a deposition and processing of the polycrystalline silicon layer and/or metal layer.

    摘要翻译： 公开了一种制造半导体器件的方法，以及根据该方法制造的器件。 该方法包括提供由硅构成的衬底; 执行浅沟槽隔离工艺以描绘nFET和pFET有源区域，并且在每个有源区域内，在衬底的表面上形成栅极结构，所述栅极结构从衬底的表面依次包括高介电常数 氧化物，由金属构成的层，由非晶硅构成的层以及由多晶硅构成的层。 提供由非晶硅组成的层，以至少在多晶硅层和/或金属层的沉积和加工过程中基本上防止高介电常数氧化物层在垂直方向上的再生长。

    Structure and Method to Fabricate Metal Gate High-K Devices
    9.
    发明申请
    Structure and Method to Fabricate Metal Gate High-K Devices 有权
    制造金属栅极高K器件的结构和方法

    公开(公告)号：US20090302396A1

    公开(公告)日：2009-12-10

    申请号：US12542855

    申请日：2009-08-18

    申请人： Tze-Chiang Chen ,  Bruce B. Doris ,  Vijay Narayanan ,  Vamsi Paruchuri

    发明人： Tze-Chiang Chen ,  Bruce B. Doris ,  Vijay Narayanan ,  Vamsi Paruchuri

    IPC分类号： H01L27/092 ,  H01L29/78

    CPC分类号： H01L21/823842 ,  H01L21/28079 ,  H01L21/823857 ,  H01L21/823878 ,  H01L29/517

    摘要： Disclosed is a method to fabricate a semiconductor device, and a device fabricated in accordance with the method. The method includes providing a substrate comprised of silicon; performing a shallow trench isolation process to delineate nFET and pFET active areas and, within each active area, forming a gate structure over a surface of the substrate, the gate structure comprising in order from the surface of the substrate, a layer of high dielectric constant oxide, a layer comprised of a metal, a layer comprised of amorphous silicon, and a layer comprised of polycrystalline silicon. The layer comprised of amorphous silicon is provided to substantially prevent regrowth of the high dielectric constant oxide layer in a vertical direction during at least a deposition and processing of the polycrystalline silicon layer and/or metal layer.

    摘要翻译： 公开了一种制造半导体器件的方法，以及根据该方法制造的器件。 该方法包括提供由硅构成的衬底; 执行浅沟槽隔离工艺以描绘nFET和pFET有源区域，并且在每个有源区域内在衬底的表面上形成栅极结构，所述栅极结构从衬底的表面依次包括高介电常数 氧化物，由金属构成的层，由非晶硅构成的层以及由多晶硅构成的层。 提供由非晶硅组成的层，以至少在多晶硅层和/或金属层的沉积和加工过程中基本上防止高介电常数氧化物层在垂直方向上的再生长。

    Structure And Method To Fabricate Metal Gate High-K Devices
    10.
    发明申请
    Structure And Method To Fabricate Metal Gate High-K Devices 失效
    制造金属栅极高K器件的结构和方法

    公开(公告)号：US20090108366A1

    公开(公告)日：2009-04-30

    申请号：US11927749

    申请日：2007-10-30

    申请人： Tze-Chiang Chen ,  Bruce B. Doris ,  Vijay Narayanan ,  Vamsi Paruchuri

    发明人： Tze-Chiang Chen ,  Bruce B. Doris ,  Vijay Narayanan ,  Vamsi Paruchuri

    IPC分类号： H01L29/51 ,  H01L21/8234

    CPC分类号： H01L21/823842 ,  H01L21/28079 ,  H01L21/823857 ,  H01L21/823878 ,  H01L29/517

    摘要： Disclosed is a method to fabricate a semiconductor device, and a device fabricated in accordance with the method. The method includes providing a substrate comprised of silicon; performing a shallow trench isolation process to delineate nFET and pFET active areas and, within each active area, forming a gate structure over a surface of the substrate, the gate structure comprising in order from the surface of the substrate, a layer of high dielectric constant oxide, a layer comprised of a metal, a layer comprised of amorphous silicon, and a layer comprised of polycrystalline silicon. The layer comprised of amorphous silicon is provided to substantially prevent regrowth of the high dielectric constant oxide layer in a vertical direction during at least a deposition and processing of the polycrystalline silicon layer and/or metal layer.

    摘要翻译： 公开了一种制造半导体器件的方法，以及根据该方法制造的器件。 该方法包括提供由硅构成的衬底; 执行浅沟槽隔离工艺以描绘nFET和pFET有源区域，并且在每个有源区域内，在衬底的表面上形成栅极结构，所述栅极结构从衬底的表面依次包括高介电常数 氧化物，由金属构成的层，由非晶硅构成的层以及由多晶硅构成的层。 提供由非晶硅组成的层，以至少在多晶硅层和/或金属层的沉积和加工过程中基本上防止高介电常数氧化物层在垂直方向上的再生长。