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18 条记录 (耗时 0.042 秒)

    Introduction of metal impurity to change workfunction of conductive electrodes
    4.
    发明申请
    Introduction of metal impurity to change workfunction of conductive electrodes 有权
    引入金属杂质来改变导电电极的功能

    公开(公告)号：US20070173008A1

    公开(公告)日：2007-07-26

    申请号：US11336727

    申请日：2006-01-20

    申请人： Michael Chudzik ,  Bruce Doris ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri ,  Yun Wang ,  Keith Wong

    发明人： Michael Chudzik ,  Bruce Doris ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri ,  Yun Wang ,  Keith Wong

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/517 ,  H01L21/28088 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Semiconductor structures, such as, for example, field effect transistors (FETs) and/or metal-oxide-semiconductor capacitor (MOSCAPs), are provided in which the workfunction of a conductive electrode stack is changed by introducing metal impurities into a metal-containing material layer which, together with a conductive electrode, is present in the electrode stack. The choice of metal impurities depends on whether the electrode is to have an n-type workfunction or a p-type workfunction. The present invention also provides a method of fabricating such semiconductor structures. The introduction of metal impurities can be achieved by codeposition of a layer containing both a metal-containing material and workfunction altering metal impurities, forming a stack in which a layer of metal impurities is present between layers of a metal-containing material, or by forming a material layer including the metal impurities above and/or below a metal-containing material and then heating the structure so that the metal impurities are introduced into the metal-containing material.

    摘要翻译： 提供半导体结构，例如场效应晶体管（FET）和/或金属氧化物半导体电容器（MOSCAP），其中通过将金属杂质引入到含金属的物质中来改变导电电极堆叠的功函数 材料层与导电电极一起存在于电极堆叠中。 金属杂质的选择取决于电极是否具有n型功函数或p型功函数。 本发明还提供一种制造这种半导体结构的方法。 金属杂质的引入可以通过共沉积含有金属的材料和改变金属杂质的功函数的层来形成，形成其中金属杂质层存在于含金属材料的层之间的叠层，或通过形成 包括在含金属材料上方和/或下面的金属杂质的材料层，然后加热该结构，使得金属杂质被引入到含金属的材料中。

    Stabilization of flatband voltages and threshold voltages in hafnium oxide based silicon transistors for CMOS
    5.
    发明申请
    Stabilization of flatband voltages and threshold voltages in hafnium oxide based silicon transistors for CMOS 有权
    用于CMOS的基于铪氧化物的硅晶体管中的平带电压和阈值电压的稳定性

    公开(公告)号：US20060244035A1

    公开(公告)日：2006-11-02

    申请号：US11118521

    申请日：2005-04-29

    申请人： Nestor Bojarczuk ,  Michael Chudzik ,  Matthew Copel ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri

    发明人： Nestor Bojarczuk ,  Michael Chudzik ,  Matthew Copel ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri

    IPC分类号： H01L29/76

    CPC分类号： H01L21/28167 ,  H01L21/28185 ,  H01L21/28194 ,  H01L29/4966 ,  H01L29/517

    摘要： The present invention provides a metal stack structure that stabilizes the flatband voltage and threshold voltages of material stacks that include a Si-containing conductor and a Hf-based dielectric. This present invention stabilizes the flatband voltages and the threshold voltages by introducing a rare earth metal-containing layer into the material stack that introduces, via electronegativity differences, a shift in the threshold voltage to the desired voltage. Specifically, the present invention provides a metal stack comprising a hafnium-based dielectric; a rare earth metal-containing layer located atop of, or within, said hafnium-based dielectric; an electrically conductive capping layer located above said hafnium-based dielectric; and a Si-containing conductor.

    摘要翻译： 本发明提供一种金属堆叠结构，其稳定包括含Si导体和Hf基电介质的材料堆叠的平带电压和阈值电压。 本发明通过将含稀土金属的层引入材料堆中来稳定平带电压和阈值电压，其通过电负性差异将阈值电压的偏移引入期望的电压。 具体地说，本发明提供一种包含铪基电介质的金属叠层; 位于所述铪基电介质的顶部或内部的含稀土金属的层; 位于所述铪基电介质上方的导电覆盖层; 和含Si导体。

    Disposable metallic or semiconductor gate spacer
    6.
    发明授权
    Disposable metallic or semiconductor gate spacer 失效
    一次性金属或半导体栅极间隔物

    公开(公告)号：US07682917B2

    公开(公告)日：2010-03-23

    申请号：US12016326

    申请日：2008-01-18

    申请人： Stephen W. Bedell ,  Michael Chudzik ,  William K. Henson ,  Naim Moumen ,  Vijay Narayanan ,  Devendra K. Sadana ,  Kathryn T. Schonenberg ,  Ghavam Shahidi

    发明人： Stephen W. Bedell ,  Michael Chudzik ,  William K. Henson ,  Naim Moumen ,  Vijay Narayanan ,  Devendra K. Sadana ,  Kathryn T. Schonenberg ,  Ghavam Shahidi

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7847 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656

    摘要： A disposable spacer is formed directly on or in close proximity to the sidewalls of a gate electrode and a gate dielectric. The disposable spacer comprises a material that scavenges oxygen such as a metal, a metal nitride, or a semiconductor material having high reactivity with oxygen. The disposable gate spacer absorbs any oxygen during subsequent high temperature processing such as a stress memorization anneal. A metal is deposited over, and reacted with, the gate electrode and source and drain regions to form metal semiconductor alloy regions. The disposable gate spacer is subsequently removed selective to the metal semiconductor alloy regions. A porous or non-porous low-k dielectric material is deposited to provide a low parasitic capacitance between the gate electrode and the source and drain regions. The gate dielectric maintains the original dielectric constant since the disposable gate spacer prevents absorption of additional oxygen during high temperature processes.

    摘要翻译： 一次性间隔物直接形成在栅极电极和栅极电介质的侧壁上或紧邻栅电极的侧壁上。 一次性间隔件包括清除氧的材料，例如金属，金属氮化物或具有高氧反应性的半导体材料。 一次性栅极间隔件在随后的高温处理例如应力记忆退火期间吸收任何氧气。 将金属沉积在栅电极和源极和漏极区上并与其反应以形成金属半导体合金区域。 一次性栅极间隔物随后被选择性地移除到金属半导体合金区域。 沉积多孔或非多孔低k电介质材料以在栅极电极和源极和漏极区域之间提供低的寄生电容。 栅极电介质保持原始介电常数，因为一次性栅极间隔物可防止在高温过程中吸收额外的氧。

    DISPOSABLE METALLIC OR SEMICONDUCTOR GATE SPACER
    7.
    发明申请
    DISPOSABLE METALLIC OR SEMICONDUCTOR GATE SPACER 失效
    可拆卸金属或半导体门间隔

    公开(公告)号：US20090186455A1

    公开(公告)日：2009-07-23

    申请号：US12016326

    申请日：2008-01-18

    申请人： Stephen W. Bedell ,  Michael Chudzik ,  William K. Henson ,  Naim Moumen ,  Vijay Narayanan ,  Devendra K. Sadana ,  Kathryn T. Schonenberg ,  Ghavam Shahidi

    发明人： Stephen W. Bedell ,  Michael Chudzik ,  William K. Henson ,  Naim Moumen ,  Vijay Narayanan ,  Devendra K. Sadana ,  Kathryn T. Schonenberg ,  Ghavam Shahidi

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/7847 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656

    摘要： A disposable spacer is formed directly on or in close proximity to the sidewalls of a gate electrode and a gate dielectric. The disposable spacer comprises a material that scavenges oxygen such as a metal, a metal nitride, or a semiconductor material having high reactivity with oxygen. The disposable gate spacer absorbs any oxygen during subsequent high temperature processing such as a stress memorization anneal. A metal is deposited over, and reacted with, the gate electrode and source and drain regions to form metal semiconductor alloy regions. The disposable gate spacer is subsequently removed selective to the metal semiconductor alloy regions. A porous or non-porous low-k dielectric material is deposited to provide a low parasitic capacitance between the gate electrode and the source and drain regions. The gate dielectric maintains the original dielectric constant since the disposable gate spacer prevents absorption of additional oxygen during high temperature processes.

    摘要翻译： 一次性间隔物直接形成在栅极电极和栅极电介质的侧壁上或紧邻栅电极的侧壁上。 一次性间隔物包括清除氧的材料，例如金属，金属氮化物或具有高氧反应性的半导体材料。 一次性栅极间隔件在随后的高温处理例如应力记忆退火期间吸收任何氧气。 将金属沉积在栅电极和源极和漏极区上并与其反应以形成金属半导体合金区域。 一次性栅极间隔物随后被选择性地移除到金属半导体合金区域。 沉积多孔或非多孔低k电介质材料以在栅极电极和源极和漏极区域之间提供低的寄生电容。 栅极电介质保持原始介电常数，因为一次性栅极间隔物可防止在高温过程中吸收额外的氧。

    HIGH DENSITY MIMCAP WITH A UNIT REPEATABLE STRUCTURE
    9.
    发明申请
    HIGH DENSITY MIMCAP WITH A UNIT REPEATABLE STRUCTURE 失效
    具有单位重复结构的高密度MIMCAP

    公开(公告)号：US20050266652A1

    公开(公告)日：2005-12-01

    申请号：US10709768

    申请日：2004-05-27

    申请人： Michael Chudzik ,  Louis Hsu ,  Joseph Shepard ,  William Tonti

    发明人： Michael Chudzik ,  Louis Hsu ,  Joseph Shepard ,  William Tonti

    IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L23/522

    CPC分类号： H01L28/91 ,  H01L23/5223 ,  H01L23/5227 ,  H01L28/87 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A structure, apparatus and method for utilizing vertically interdigitated electrodes serves to increase the capacitor area surface while maintaining a minimal horizontal foot print. Since capacitance is proportional to the surface area the structure enables continual use of current dielectric materials such as Si3N4 at current thicknesses. In a second embodiment of the interdigitated MIMCAP structure the electrodes are formed in a spiral fashion which serves to increase the physical strength of the MIMCAP. Also included is a spiral shaped capacitor electrode which lends itself to modular design by offering a wide range of discrete capacitive values easily specified by the circuit designer.

    摘要翻译： 用于利用垂直交错电极的结构，装置和方法用于增加电容器面积，同时保持最小的水平脚印。 由于电容与表面积成比例，因此该结构能够连续使用当前厚度的当前介电材料，例如Si 3 N 4。 在叉指MIMCAP结构的第二实施例中，电极以螺旋方式形成，其用于增加MIMCAP的物理强度。 还包括螺旋形电容器电极，其通过提供电路设计者容易指定的宽范围的离散电容值来适应模块化设计。

    RESIDUE FREE PATTERNED LAYER FORMATION METHOD APPLICABLE TO CMOS STRUCTURES
    10.
    发明申请
    RESIDUE FREE PATTERNED LAYER FORMATION METHOD APPLICABLE TO CMOS STRUCTURES 有权
    适用于CMOS结构的残留层形成方法

    公开(公告)号：US20080280404A1

    公开(公告)日：2008-11-13

    申请号：US11746759

    申请日：2007-05-10

    申请人： Michael Chudzik ,  Bruce B. Doris ,  William K. Henson ,  Hongwen Yan ,  Ying Zhang

    发明人： Michael Chudzik ,  Bruce B. Doris ,  William K. Henson ,  Hongwen Yan ,  Ying Zhang

    IPC分类号： H01L21/28 ,  H01L21/02 ,  H01L21/311

    CPC分类号： H01L29/045 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28097 ,  H01L21/31138 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/84

    摘要： A method for forming a microelectronic structure uses a mask layer located over a target layer. The target layer may be etched while using the mask layer as an etch mask to form an end tapered target layer from the target layer. An additional target layer may be formed over the end tapered target layer and masked with an additional mask layer. The additional target layer may be etched to form a patterned additional target layer separated from the end tapered target layer and absent an additional target layer residue adjacent the end tapered target layer. The method is useful for fabricating CMOS structures including nFET and pFET gate electrodes comprising different NFET and pFET gate electrode materials.

    摘要翻译： 形成微电子结构的方法使用位于目标层上的掩模层。 可以使用掩模层作为蚀刻掩模来蚀刻目标层，以从目标层形成端部锥形目标层。 可以在端部锥形目标层上形成另外的目标层，并用附加掩模层掩模。 可以蚀刻附加目标层以形成与端部锥形目标层分离的图案化附加目标层，并且不存在与端部锥形目标层相邻的附加靶层残余物。 该方法对于制造包括nFET和pFET栅电极的CMOS结构是有用的，其包括不同的NFET和pFET栅电极材料。