公开(公告)号：US20080167829A1

公开(公告)日：2008-07-10

申请号：US11970294

申请日：2008-01-07

申请人： Allen Park ,  Peter Rose ,  Ellis Chang ,  Brian Duffy ,  Mark McCord ,  Gordon Abbott

发明人： Allen Park ,  Peter Rose ,  Ellis Chang ,  Brian Duffy ,  Mark McCord ,  Gordon Abbott

IPC分类号： G01N37/00

CPC分类号： G06T7/0004 ,  G01N21/8851 ,  G01N21/956 ,  G01R31/2894 ,  G06T2207/30148

摘要： Various methods and systems for using electrical information for a device being fabricated on a wafer to perform one or more defect-related functions are provided. One computer-implemented method includes using electrical information for a device being fabricated on a wafer to perform one or more defect-related functions. The one or more defect-related functions include one or more post-mask, defect-related functions.

摘要翻译： 提供了用于对在晶片上制造的器件使用电信息以执行一个或多个缺陷相关功能的各种方法和系统。 一种计算机实现的方法包括使用在晶片上制造的器件的电信息来执行一个或多个缺陷相关功能。 一个或多个缺陷相关功能包括一个或多个后掩模缺陷相关功能。

公开(公告)号：US08194968B2

公开(公告)日：2012-06-05

申请号：US11970294

申请日：2008-01-07

申请人： Allen Park ,  Peter Rose ,  Ellis Chang ,  Brian Duffy ,  Mark McCord ,  Gordon Abbott

发明人： Allen Park ,  Peter Rose ,  Ellis Chang ,  Brian Duffy ,  Mark McCord ,  Gordon Abbott

IPC分类号： G06K9/00

CPC分类号： G06T7/0004 ,  G01N21/8851 ,  G01N21/956 ,  G01R31/2894 ,  G06T2207/30148

摘要： Various methods and systems for using electrical information for a device being fabricated on a wafer to perform one or more defect-related functions are provided. One computer-implemented method includes using electrical information for a device being fabricated on a wafer to perform one or more defect-related functions. The one or more defect-related functions include one or more post-mask, defect-related functions.

摘要翻译： 提供了用于对在晶片上制造的器件使用电信息以执行一个或多个缺陷相关功能的各种方法和系统。 一种计算机实现的方法包括使用在晶片上制造的器件的电信息来执行一个或多个缺陷相关功能。 一个或多个缺陷相关功能包括一个或多个后掩模缺陷相关功能。

公开(公告)号：US08923600B2

公开(公告)日：2014-12-30

申请号：US12534547

申请日：2009-08-03

申请人： Khurram Zafar ,  Sagar Kekare ,  Ellis Chang ,  Allen Park ,  Peter Rose

发明人： Khurram Zafar ,  Sagar Kekare ,  Ellis Chang ,  Allen Park ,  Peter Rose

IPC分类号： G06K9/00 ,  G06F17/50 ,  G03F1/84

CPC分类号： G06T7/0006 ,  G03F1/84 ,  G06F17/5081 ,  G06T7/0008 ,  G06T2207/20076 ,  G06T2207/30148

摘要： Various methods and systems for utilizing design data in combination with inspection data are provided. One computer-implemented method for binning defects detected on a wafer includes comparing portions of design data proximate positions of the defects in design data space. The method also includes determining if the design data in the portions is at least similar based on results of the comparing step. In addition, the method includes binning the defects in groups such that the portions of the design data proximate the positions of the defects in each of the groups are at least similar. The method further includes storing results of the binning step in a storage medium.

摘要翻译： 提供了与检测数据结合使用设计数据的各种方法和系统。 用于对在晶片上检测到的缺陷进行合并的计算机实现的方法包括将设计数据的部分靠近设计数据空间中的缺陷的位置进行比较。 该方法还包括基于比较步骤的结果确定部分中的设计数据是否至少相似。 此外，该方法包括将组中的缺陷合并成使得设计数据中靠近每个组中的缺陷的位置的部分至少相似。 该方法还包括将合并步骤的结果存储在存储介质中。

公开(公告)号：US20090297019A1

公开(公告)日：2009-12-03

申请号：US12534547

申请日：2009-08-03

申请人： Khurram Zafar ,  Sagar Kekare ,  Ellis Chang ,  Allen Park ,  Peter Rose

发明人： Khurram Zafar ,  Sagar Kekare ,  Ellis Chang ,  Allen Park ,  Peter Rose

IPC分类号： G06K9/00

CPC分类号： G06T7/0006 ,  G03F1/84 ,  G06F17/5081 ,  G06T7/0008 ,  G06T2207/20076 ,  G06T2207/30148

摘要： Various methods and systems for utilizing design data in combination with inspection data are provided. One computer-implemented method for binning defects detected on a wafer includes comparing portions of design data proximate positions of the defects in design data space. The method also includes determining if the design data in the portions is at least similar based on results of the comparing step. In addition, the method includes binning the defects in groups such that the portions of the design data proximate the positions of the defects in each of the groups are at least similar. The method further includes storing results of the binning step in a storage medium.

摘要翻译： 提供了与检测数据结合使用设计数据的各种方法和系统。 用于对在晶片上检测到的缺陷进行合并的计算机实现的方法包括将设计数据的部分靠近设计数据空间中的缺陷的位置进行比较。 该方法还包括基于比较步骤的结果确定部分中的设计数据是否至少相似。 此外，该方法包括将组中的缺陷合并成使得设计数据中靠近每个组中的缺陷的位置的部分至少相似。 该方法还包括将合并步骤的结果存储在存储介质中。

公开(公告)号：US07570796B2

公开(公告)日：2009-08-04

申请号：US11561659

申请日：2006-11-20

申请人： Khurram Zafar ,  Sagar Kekare ,  Ellis Chang ,  Allen Park ,  Peter Rose

发明人： Khurram Zafar ,  Sagar Kekare ,  Ellis Chang ,  Allen Park ,  Peter Rose

IPC分类号： G06K9/00

CPC分类号： G06T7/0006 ,  G03F1/84 ,  G06F17/5081 ,  G06T7/0008 ,  G06T2207/20076 ,  G06T2207/30148

摘要： Various methods and systems for utilizing design data in combination with inspection data are provided. One computer-implemented method for binning defects detected on a wafer includes comparing portions of design data proximate positions of the defects in design data space. The method also includes determining if the design data in the portions is at least similar based on results of the comparing step. In addition, the method includes binning the defects in groups such that the portions of the design data proximate the positions of the defects in each of the groups are at least similar. The method further includes storing results of the binning step in a storage medium.

摘要翻译： 提供了与检测数据结合使用设计数据的各种方法和系统。 用于对在晶片上检测到的缺陷进行合并的计算机实现的方法包括将设计数据的部分靠近设计数据空间中的缺陷的位置进行比较。 该方法还包括基于比较步骤的结果确定部分中的设计数据是否至少相似。 此外，该方法包括将组中的缺陷合并成使得设计数据中靠近每个组中的缺陷的位置的部分至少相似。 该方法还包括将合并步骤的结果存储在存储介质中。

公开(公告)号：US20070288219A1

公开(公告)日：2007-12-13

申请号：US11561659

申请日：2006-11-20

申请人： Khurram Zafar ,  Sagar Kekare ,  Ellis Chang ,  Allen Park ,  Peter Rose

发明人： Khurram Zafar ,  Sagar Kekare ,  Ellis Chang ,  Allen Park ,  Peter Rose

IPC分类号： G06F17/50

CPC分类号： G06T7/0006 ,  G03F1/84 ,  G06F17/5081 ,  G06T7/0008 ,  G06T2207/20076 ,  G06T2207/30148

摘要： Various methods and systems for utilizing design data in combination with inspection data are provided. One computer-implemented method for binning defects detected on a wafer includes comparing portions of design data proximate positions of the defects in design data space. The method also includes determining if the design data in the portions is at least similar based on results of the comparing step. In addition, the method includes binning the defects in groups such that the portions of the design data proximate the positions of the defects in each of the groups are at least similar. The method further includes storing results of the binning step in a storage medium.

摘要翻译： 提供了与检测数据结合使用设计数据的各种方法和系统。 用于对在晶片上检测到的缺陷进行合并的计算机实现的方法包括将设计数据的部分靠近设计数据空间中的缺陷的位置进行比较。 该方法还包括基于比较步骤的结果确定部分中的设计数据是否至少相似。 此外，该方法包括将组中的缺陷合并成使得设计数据中靠近每个组中的缺陷的位置的部分至少相似。 该方法还包括将合并步骤的结果存储在存储介质中。

公开(公告)号：US20110170091A1

公开(公告)日：2011-07-14

申请号：US12984679

申请日：2011-01-05

申请人： Ellis Chang ,  Amir Widmann ,  Allen Park

发明人： Ellis Chang ,  Amir Widmann ,  Allen Park

IPC分类号： G01N21/00

CPC分类号： G01N21/9501 ,  G01N21/95607 ,  G01N2021/8822 ,  G03F7/70633 ,  G03F7/7065 ,  H01L22/12 ,  H01L2924/0002 ,  H01L2924/00

摘要： Inspection guided overlay metrology may include performing a pattern search in order to identify a predetermined pattern on a semiconductor wafer, generating a care area for all instances of the predetermined pattern on the semiconductor wafer, identifying defects within generated care areas by performing an inspection scan of each of the generated care areas, wherein the inspection scan includes a low-threshold or a high sensitivity inspection scan, identifying overlay sites of the predetermined pattern of the semiconductor wafer having a measured overlay error larger than a selected overlay specification utilizing a defect inspection technique, comparing location data of the identified defects of a generated care area to location data of the identified overlay sites within the generated care area in order to identify one or more locations wherein the defects are proximate to the identified overlay sites, and generating a metrology sampling plan based on the identified locations.

摘要翻译： 检查引导覆盖度量可以包括执行图案搜索以便识别半导体晶片上的预定图案，为半导体晶片上的预定图案的所有实例生成护理区域，通过执行检查扫描来检查所产生的护理区域内的缺陷 每个生成的护理区域，其中检查扫描包括低阈值或高灵敏度检查扫描，识别具有大于使用缺陷检查技术的所选覆盖规格的测量的覆盖误差的半导体晶片的预定图案的覆盖位置 将生成的护理区域的所识别的缺陷的位置数据与生成的护理区域内的所识别的覆盖位置的位置数据进行比较，以便识别其中缺陷接近所识别的覆盖位置的一个或多个位置，以及生成计量取样 基于确定的位置进行计划。

公开(公告)号：US08559001B2

公开(公告)日：2013-10-15

申请号：US12984679

申请日：2011-01-05

申请人： Ellis Chang ,  Amir Widmann ,  Allen Park

发明人： Ellis Chang ,  Amir Widmann ,  Allen Park

IPC分类号： G01N21/00 ,  G01R31/26

CPC分类号： G01N21/9501 ,  G01N21/95607 ,  G01N2021/8822 ,  G03F7/70633 ,  G03F7/7065 ,  H01L22/12 ,  H01L2924/0002 ,  H01L2924/00

摘要： Inspection guided overlay metrology may include performing a pattern search in order to identify a predetermined pattern on a semiconductor wafer, generating a care area for all instances of the predetermined pattern on the semiconductor wafer, identifying defects within generated care areas by performing an inspection scan of each of the generated care areas, wherein the inspection scan includes a low-threshold or a high sensitivity inspection scan, identifying overlay sites of the predetermined pattern of the semiconductor wafer having a measured overlay error larger than a selected overlay specification utilizing a defect inspection technique, comparing location data of the identified defects of a generated care area to location data of the identified overlay sites within the generated care area in order to identify one or more locations wherein the defects are proximate to the identified overlay sites, and generating a metrology sampling plan based on the identified locations.

公开(公告)号：US09087367B2

公开(公告)日：2015-07-21

申请号：US13601891

申请日：2012-08-31

申请人： Ellis Chang ,  Michael J. Van Riet ,  Allen Park ,  Khurram Zafar ,  Santosh Bhattacharyya

发明人： Ellis Chang ,  Michael J. Van Riet ,  Allen Park ,  Khurram Zafar ,  Santosh Bhattacharyya

IPC分类号： G06K9/62 ,  G06T7/00

CPC分类号： G06T7/001 ,  G06T7/74 ,  G06T2207/30148

摘要： Methods and systems for determining design coordinates for defects detected on a wafer are provided. One method includes aligning a design for a wafer to defect review tool images for defects detected in multiple swaths on the wafer by an inspection tool, determining a position of each of the defects in design coordinates based on results of the aligning, separately determining a defect position offset for each of the multiple swaths based on the swath in which each of the defects was detected (swath correction factor), the design coordinates for each of the defects, and a position for each of the defects determined by the inspection tool, and determining design coordinates for the other defects detected in the multiple swaths by the inspection tool by applying the appropriate swath correction factor to those defects.

摘要翻译： 提供了用于确定在晶片上检测到的缺陷的设计坐标的方法和系统。 一种方法包括对准晶片的设计以通过检查工具对晶片上的多个条带中检测到的缺陷来检查工具图像，基于对准的结果确定每个缺陷在设计坐标中的位置，分别确定缺陷 基于检测到每个缺陷的条带（条纹校正因子），每个缺陷的设计坐标以及由检查工具确定的每个缺陷的位置，针对每个多个条带的位置偏移，以及 通过对这些缺陷应用适当的条纹校正因子来确定检测工具在多个条中检测到的其他缺陷的设计坐标。

公开(公告)号：US08989479B2

公开(公告)日：2015-03-24

申请号：US13381696

申请日：2011-08-01

申请人： Lisheng Gao ,  Kenong Wu ,  Allen Park ,  Ellis Chang ,  Khurram Zafar ,  Junqing Huang ,  Ping Gu ,  Christopher Maher ,  Grace H. Chen ,  Songnian Rong ,  Liu-Ming Wu

发明人： Lisheng Gao ,  Kenong Wu ,  Allen Park ,  Ellis Chang ,  Khurram Zafar ,  Junqing Huang ,  Ping Gu ,  Christopher Maher ,  Grace H. Chen ,  Songnian Rong ,  Liu-Ming Wu

IPC分类号： G06K9/00 ,  G06T7/00

CPC分类号： G06T7/001 ,  G06T2207/10061 ,  G06T2207/20021 ,  G06T2207/20056 ,  G06T2207/30148

摘要： The present invention includes searching imagery data in order to identify one or more patterned regions on a semiconductor wafer, generating one or more virtual Fourier filter (VFF) working areas, acquiring an initial set of imagery data from the VFF working areas, defining VFF training blocks within the identified patterned regions of the VFF working areas utilizing the initial set of imagery data, wherein each VFF training block is defined to encompass a portion of the identified patterned region displaying a selected repeating pattern, calculating an initial spectrum for each VFF training block utilizing the initial set of imagery data from the VFF training blocks, and generating a VFF for each training block by identifying frequencies of the initial spectrum having maxima in the frequency domain, wherein the VFF is configured to null the magnitude of the initial spectrum at the frequencies identified to display spectral maxima.

摘要翻译： 本发明包括搜索图像数据以便识别半导体晶片上的一个或多个图案化区域，生成一个或多个虚拟傅立叶滤波器（VFF）工作区域，从VFF工作区域获取初始图像数据集，定义VFF训练 利用初始的图像数据集，在VFF工作区域的所识别的图案化区域内的块，其中每个VFF训练块被定义为包含所识别的图案化区域的一部分，显示所选择的重复模式，计算每个VFF训练块的初始频谱 利用来自VFF训练块的初始图像数据组，以及通过识别在频域中具有最大值的初始频谱的频率，为每个训练块生成VFF，其中VFF被配置为在 识别出显示频谱最大值的频率。