Flexibly scalable charge balanced vertical semiconductor power devices with a super-junction structure
    2.
    发明授权
    Flexibly scalable charge balanced vertical semiconductor power devices with a super-junction structure 有权
    具有超结结构的灵活可扩展的电荷平衡垂直半导体功率器件

    公开(公告)号:US09368614B2

    公开(公告)日:2016-06-14

    申请号:US13954909

    申请日:2013-07-30

    发明人: François Hébert

    摘要: This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of deep trenches. The deep trenches are filled with an epitaxial layer thus forming a top epitaxial layer covering areas above a top surface of the deep trenches covering over the semiconductor substrate. The semiconductor power device further includes a plurality of transistor cells disposed in the top epitaxial layer whereby a device performance of the semiconductor power device is dependent on a depth of the deep trenches and not dependent on a thickness of the top epitaxial layer. Each of the plurality of transistor cells includes a trench DMOS transistor cell having a trench gate opened through the top epitaxial layer and filled with a gate dielectric material.

    摘要翻译: 本发明公开了一种设置在半导体衬底中的半导体功率器件,半导体衬底具有多个深沟槽。 深沟槽填充有外延层,从而形成覆盖半导体衬底上的深沟槽顶表面上方的区域的顶部外延层。 半导体功率器件还包括设置在顶部外延层中的多个晶体管单元,由此半导体功率器件的器件性能取决于深沟槽的深度,而不依赖于顶部外延层的厚度。 多个晶体管单元中的每一个包括沟槽DMOS晶体管单元,其沟槽栅极通过顶部外延层开口并且填充有栅极电介质材料。

    Super-self-aligned Trench-DMOS structure and method
    3.
    发明授权
    Super-self-aligned Trench-DMOS structure and method 有权
    超自对准沟槽DMOS结构和方法

    公开(公告)号:US08785280B2

    公开(公告)日:2014-07-22

    申请号:US13709614

    申请日:2012-12-10

    发明人: François Hébert

    IPC分类号: H01L21/336

    摘要: A body layer is formed in an epitaxial layer and a gate electrode formed in a trench in the body and epitaxial layer. A gate insulator is disposed along a sidewall of the gate electrode between the gate electrode and the source, between the gate electrode and the P-body and between the gate electrode and the epitaxial layer. A cap insulator is disposed on top of the gate electrode. A doped spacer is disposed along a sidewall of the source and a sidewall of the gate insulator. The body layer next to the polysilicon spacer is etched back below the bottom of the polysilicon spacer. Dopants are diffused from the spacer to form the source region.

    摘要翻译: 主体层形成在外延层中,形成在主体和外延层中的沟槽中的栅电极。 栅极绝缘体沿着栅极电极的侧壁设置在栅电极和源极之间,在栅电极和P体之间以及栅电极和外延层之间。 盖绝缘体设置在栅电极的顶部。 掺杂间隔物沿着源极的侧壁和栅极绝缘体的侧壁设置。 多晶硅间隔物旁边的主体层被蚀刻回多晶硅间隔物的底部之下。 掺杂剂从间隔物扩散以形成源区。

    DEVICE STRUCTURE AND MANUFACTURING METHOD USING HDP DEPOSITED SOURCE-BODY IMPLANT BLOCK
    4.
    发明申请
    DEVICE STRUCTURE AND MANUFACTURING METHOD USING HDP DEPOSITED SOURCE-BODY IMPLANT BLOCK 审中-公开
    使用HDP沉积源体植入块的装置结构和制造方法

    公开(公告)号:US20160322469A1

    公开(公告)日:2016-11-03

    申请号:US14702695

    申请日:2015-05-02

    摘要: This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.

    摘要翻译: 本发明公开了一种半导体功率器件。 沟槽半导体功率器件包括从半导体衬底的顶表面开口的沟槽栅极,被包围在设置在衬底底表面上的漏区以上的顶表面附近的体区中的源极区围绕。 所述半导体功率器件还包括植入离子块,所述植入离子块设置在所述身体区域旁边的台面区域的上表面上,所述植入离子块具有基本上大于0.3微米的厚度,用于阻挡体注入离子和源离子进入台面区域 从而可以减少用于制造半导体功率器件的掩模。