公开(公告)号：US09412436B1

公开(公告)日：2016-08-09

申请号：US14247075

申请日：2014-04-07

Applicant: Altera Corporation

Inventor： Irfan Rahim ,  Andy L. Lee ,  Jeffrey T. Watt ,  William Bradley Vest

IPC: G11C11/00 ,  G11C11/412 ,  G11C5/06

CPC classification number: G11C11/412 ,  G11C5/005 ,  G11C5/06 ,  G11C8/16 ,  G11C11/4125

Abstract: Memory elements are provided that exhibit immunity to soft error upset events when subjected to radiation strikes such as high-energy atomic particle strikes. Each memory element may each have four inverter-like transistor pairs that form a bistable element, a pair of address transistors, and a pair of relatively weak transistors connected between two of the inverters that create a common output node which is resistant to rapid changes to its state. The transistors may be connected in a pattern that forms a bistable memory element that is resistant to soft error upset events due to radiation strikes. Data may be loaded into and read out of the memory element using the address transistor pair.

Abstract translation: 提供了存储器元件，当受到诸如高能量原子粒子撞击的辐射攻击时，其表现出对软错误失调事件的抗扰性。 每个存储元件可以各自具有形成双稳态元件，一对地址晶体管和连接在两个逆变器之间的一对相对较弱的晶体管的四个逆变器状晶体管对，其形成公共输出节点，其抵抗快速变化 它的状态。 晶体管可以以形成双稳态存储器元件的图案连接，该双稳态存储器元件由于辐射打击而抵抗软错误不正常事件。 可以使用地址晶体管对将数据加载到存储器元件中并从存储器元件读出。

公开(公告)号：US09166052B1

公开(公告)日：2015-10-20

申请号：US14576610

申请日：2014-12-19

Applicant: Altera Corporation

Inventor： Chun Lee Ler ,  Shuxian Chen ,  Jeffrey T. Watt

IPC: H03H11/16 ,  H01L29/78 ,  H01L27/06 ,  H01L29/93

CPC classification number: H01L29/7855 ,  H01L27/0629 ,  H01L29/93 ,  H03H7/185 ,  H03H7/20

Abstract: A multiple gate semiconductor structure is disclosed having a thin segment of semiconductor with first and second major surfaces that are opposite one another, a first gate on the first major surface of the segment, a second gate on the second major surface of the segment opposite the first gate, a first differential input coupled to the first gate, and a second differential input coupled to the second gate. Preferably the semiconductor structure is symmetrical about a plane that extends through the thin segment between the first and second major surfaces. When a first voltage of a first polarity is applied to the first input and a second voltage of the same magnitude as that of the first voltage but of opposite polarity is applied to the second input, a virtual ground is established in the structure near its center of the segment.

Abstract translation: 公开了一种多栅极半导体结构，其具有薄的半导体段，其具有彼此相对的第一和第二主表面，该段的第一主表面上的第一栅极，与该区段的第二主表面相对的第二栅极 第一栅极，耦合到第一栅极的第一差分输入和耦合到第二栅极的第二差分输入。 优选地，半导体结构关于延伸穿过第一和第二主表面之间的细段的平面对称。 当将第一极性的第一电压施加到第一输入端并且与第一电压相同大小的第二电压施加到第二输入时，在靠近其中心的结构中建立虚拟地 的段。

公开(公告)号：US08873278B1

公开(公告)日：2014-10-28

申请号：US13732737

申请日：2013-01-02

Applicant: Altera Corporation

Inventor： Yanzhong Xu ,  Jeffrey T. Watt

IPC: G11C11/00

CPC classification number: G11C11/4125 ,  H03K19/0033

Abstract: Memory elements are provided that exhibit immunity to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements may each have ten transistors. To overcome difficulties in writing data into the memory elements, signal strengths for one or more of the signals provided to the array may be adjusted. There may be two positive power supply voltages that are used in powering each memory element. One of the power supply voltages may be temporarily lowered relative to the other power supply voltage to enhance write margin during data loading operations. Other signal strengths that may be adjusted in this way include other power supply signals, data signal levels, address and clear signal magnitudes, and ground signal strengths. Adjustable power supply circuitry and data read-write control circuitry may be used in making these signal strength adjustments.

Abstract translation: 提供了存储元件，当受到高能原子粒子撞击时，表现出对软错误失调事件的抵抗力。 存储元件可以各自具有十个晶体管。 为了克服将数据写入存储元件的困难，可以调整提供给阵列的一个或多个信号的信号强度。 在为每个存储元件供电时使用两个正电源电压。 电源电压之一可能相对于另一个电源电压暂时降低，以增强数据加载操作期间的写入裕度。 可以以这种方式调整的其他信号强度包括其他电源信号，数据信号电平，地址和清除信号幅度以及接地信号强度。 可调电源电路和数据读写控制电路可用于进行这些信号强度的调整。

公开(公告)号：US10114068B1

公开(公告)日：2018-10-30

申请号：US13973822

申请日：2013-08-22

Applicant: Altera Corporation

Inventor： Christopher Sun Young Chen ,  Jeffrey T. Watt

IPC: G01R31/28

Abstract: An integrated circuit capable of monitoring aging effects on an integrated circuit device is disclosed. The integrated circuit includes a control circuit that obtains a clock signal at different frequencies. A sense circuit may receive the clock signal. First and second control signals may be asserted on the integrated circuit with the control circuit. The first control signal may activate a stress mode, and the second control signal may activate a measurement mode. During stress mode, the sense circuit may receive the clock signal. Any changes in predetermined electrical parameters of one or more transistors in the sense circuit may be monitored and measured during the measurement mode. Aging compensation may be performed when aging effect is detected on the sense circuit.

公开(公告)号：US09633872B2

公开(公告)日：2017-04-25

申请号：US13752808

申请日：2013-01-29

Applicant: Altera Corporation

Inventor： Shuxian Chen ,  Jeffrey T. Watt

IPC: H01L21/50 ,  H01L23/52 ,  H01L25/18 ,  H01L23/528 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L21/50 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5286 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/15311

Abstract: An integrated circuit package may include a substrate and an interposer. The interposer is disposed over the substrate. The interposer may include embedded switching elements that may be used to receive different power supply signals. An integrated circuit with multiple logic blocks is disposed over the substrate. The switching elements embedded in the interposer may be used to select a power supply signal from the power supply signals and may be used to provide at least one circuit block in the integrated circuit with a selected power supply signal.

公开(公告)号：US09520182B2

公开(公告)日：2016-12-13

申请号：US14092298

申请日：2013-11-27

Applicant: Altera Corporation

Inventor： Lin-Shih Liu ,  Mark T. Chan ,  Yanzhong Xu ,  Irfan Rahim ,  Jeffrey T. Watt

IPC: G11C11/00 ,  G11C11/52 ,  H01L27/10 ,  G11C13/02 ,  G11C23/00 ,  H01H59/00 ,  B82Y10/00 ,  H01H1/00 ,  H01H1/20

CPC classification number: G11C11/52 ,  B82Y10/00 ,  G11C13/025 ,  G11C23/00 ,  H01H1/0094 ,  H01H1/20 ,  H01H59/0009 ,  H01L27/101 ,  H01L27/11

Abstract: Integrated circuits with memory elements are provided. An integrated circuit may include logic circuitry formed in a first portion having complementary metal-oxide-semiconductor (CMOS) devices and may include at least a portion of the memory elements and associated memory circuitry formed in a second portion having nano-electromechanical (NEM) relay devices. The NEM and CMOS devices may be interconnected through vias in a dielectric stack. Devices in the first and second portions may receive respective power supply voltages. In one suitable arrangement, the memory elements may include two relay switches that provide nonvolatile storage characteristics and soft error upset (SEU) immunity. In another suitable arrangement, the memory elements may include first and second cross-coupled inverting circuits. The first inverting circuit may include relay switches, whereas the second inverting circuit includes only CMOS transistors. Memory elements configured in this way may be used to provide volatile storage characteristics and SEU immunity.

公开(公告)号：US08928382B1

公开(公告)日：2015-01-06

申请号：US13832619

申请日：2013-03-15

Applicant: Altera Corporation

Inventor： Chun Lee Ler ,  Shuxian Chen ,  Jeffrey T. Watt

IPC: H03H11/16 ,  H01L29/78 ,  G05F3/02 ,  H03H11/20

CPC classification number: H01L29/7855 ,  H01L27/0629 ,  H01L29/93 ,  H03H7/185 ,  H03H7/20

Abstract: A multiple gate semiconductor structure is disclosed having a thin segment of semiconductor with first and second major surfaces that are opposite one another, a first gate on the first major surface of the segment, a second gate on the second major surface of the segment opposite the first gate, a first differential input coupled to the first gate, and a second differential input coupled to the second gate. Preferably the semiconductor structure is symmetrical about a plane that extends through the thin segment between the first and second major surfaces. When a first voltage of a first polarity is applied to the first input and a second voltage of the same magnitude as that of the first voltage but of opposite polarity is applied to the second input, a virtual ground is established in the structure near its center of the segment.

公开(公告)号：US08823135B2

公开(公告)日：2014-09-02

申请号：US14040300

申请日：2013-09-27

Applicant: Altera Corporation

Inventor： Shuxian Chen ,  Jeffrey T. Watt

IPC: H01L29/92

CPC classification number: H01L29/92 ,  H01L23/5225 ,  H01L23/552 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A shielding structure for transmission lines comprises first and second comb-like structures defined in a first metallization layer on an integrated circuit, the teeth of each comb-like structure extending toward the other comb-like structure; a first plurality of electrically conducting vias extending upward from the first comb-like structure; a second plurality of electrically conducting vias extending upward from the second comb-like structure; first and second planar structures in a second metallization layer above the first metallization layer; a third plurality of electrically conducting vias extending downward from the first planar structure toward the first plurality of electrically conducting vias; and a fourth plurality of electrically conducting vias extending downward from the second planar structure toward the second plurality of electrically conducting vias. The comb-like structures, the planar structures and the first, second, third, and fourth electrically conducting vias are all at substantially the same potential, preferably ground.

Abstract translation: 用于传输线的屏蔽结构包括在集成电路上的第一金属化层中限定的第一和第二梳状结构，每个梳状结构的齿朝向另一梳状结构延伸; 从所述第一梳状结构向上延伸的第一多个导电通孔; 从所述第二梳状结构向上延伸的第二多个导电通孔; 在第一金属化层上方的第二金属化层中的第一和第二平面结构; 从所述第一平面结构朝向所述第一多个导电通孔向下延伸的第三多个导电通孔; 以及从第二平面结构朝向第二多个电导通孔向下延伸的第四多个导电通孔。 梳状结构，平面结构以及第一，第二，第三和第四导电通孔全部处于基本上相同的电位，优选接地。

公开(公告)号：US20140218068A1

公开(公告)日：2014-08-07

申请号：US14247030

申请日：2014-04-07

Applicant: Altera Corporation

Inventor： Andy L. Lee ,  Jeffrey T. Watt

IPC: H03K19/173

CPC classification number: H03K19/173 ,  G11C5/005 ,  H01L27/0207 ,  H03K19/1736 ,  H03K19/17784

Abstract: Hardened programmable logic devices are provided with programmable circuitry. The programmable circuitry may be hardwired to implement a custom logic circuit. Generic fabrication masks may be used to form the programmable circuitry and may be used in manufacturing a product family of hardened programmable logic devices, each of which may implement a different custom logic circuit. Custom fabrication masks may be used to hardwire the programmable circuitry to implement a specific custom logic circuit. The programmable circuitry may be hardwired in such a way that signal timing characteristics of a hardened programmable logic device that implements a custom logic circuit may match the signal timing characteristics of a programmable logic device that implements the same custom logic circuit using configuration data.

Abstract translation: 硬化可编程逻辑器件提供有可编程电路。 可编程电路可以是硬连线的，以实现定制逻辑电路。 可以使用通用制造掩模来形成可编程电路，并且可以用于制造硬化的可编程逻辑器件的产品系列，每一个可以实现不同的定制逻辑电路。 可以使用定制制造掩模来硬编程电路来实现特定的定制逻辑电路。 可编程电路可以是硬连线的，使得实现定制逻辑电路的硬化可编程逻辑器件的信号定时特性可以匹配使用配置数据实现相同定制逻辑电路的可编程逻辑器件的信号定时特性。

公开(公告)号：US08750026B1

公开(公告)日：2014-06-10

申请号：US13923276

申请日：2013-06-20

Applicant: Altera Corporation

Inventor： Jun Liu ,  Yanzhong Xu ,  Shankar Sinha ,  Shih-Lin S. Lee ,  Jeffrey Xiaoqi Tung ,  Albert Ratnakumar ,  Qi Xiang ,  Irfan Rahim ,  Andy L. Lee ,  Jeffrey T. Watt ,  Srinivas Perisetty

IPC: G11C11/412 ,  G11C7/10 ,  G11C8/16

CPC classification number: G11C11/412

Abstract: Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.

Abstract translation: 不对称晶体管可以通过在晶体管的一个源极 - 漏极端子上而不是另一个产生凹穴注入来形成。 也可以使用具有不同功函数的第一和第二栅极导体的双栅结构来形成非对称晶体管。 可以通过堆叠相同通道类型的两个晶体管串联形成堆叠晶体管。 两个晶体管中的每一个的源极 - 漏极端子之一连接到公共节点。 两个晶体管的栅极也连接在一起。 两个晶体管可以具有不同的阈值电压。 位于堆叠晶体管中较高的晶体管的阈值电压可以具有比堆叠晶体管中的另一个晶体管更低的阈值电压。 堆叠的晶体管可用于减少诸如存储器单元的电路中的漏电流。 不对称晶体管也可用于存储器单元中以减少泄漏。