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    HIGH RESOLUTION OUTPUT DRIVER
    3.
    发明申请
    HIGH RESOLUTION OUTPUT DRIVER 有权
    高分辨率输出驱动器

    公开(公告)号：US20120147944A1

    公开(公告)日：2012-06-14

    申请号：US13391383

    申请日：2010-09-14

    申请人： Amir Amirkhany ,  Chaofeng Huang ,  Kambiz Kaviani ,  Wayne D. Dettloof ,  Kun-Yung Chang

    发明人： Amir Amirkhany ,  Chaofeng Huang ,  Kambiz Kaviani ,  Wayne D. Dettloof ,  Kun-Yung Chang

    IPC分类号： H04L27/01

    CPC分类号： H03K19/0005 ,  H03K19/017581 ,  H03M1/1061 ,  H03M1/745 ,  H04L25/0278 ,  H04L25/0288 ,  H04L25/03343

    摘要： High resolution output drivers having a relatively small number of sub-driver branches or slices each having nominal impedances substantially larger than a quantization step and that incrementally differ from one another by an impedance step substantially smaller than a quantization step. In one implementation, such “differential” or “non-uniform” sub-driver slices implement respective elements of an n choose k equalizer, with each such differential sub-driver slice being implemented by a uniform-element impedance calibration DAC. In another implementation, each component of a uniform-slice equalizer is implemented by a differential-slice impedance calibration DAC, and in yet another implementation, each component of a differential-slice equalizer is implemented by a differential-slice impedance calibration DAC. In an additional set of implementations, equalization and impedance calibration functions are implemented bilaterally in respective parallel sets of driver branches, rather than in the nested “DAC within a DAC” arrangement of the hierarchical implementations. Through such bilateral arrangement, multiplication of the equalizer and calibrator quantizations is avoided, thereby lowering the total number of sub-driver slices required to meet the specified ranges and resolutions.

    摘要翻译： 具有相对较少数量的子驱动器分支或切片的高分辨率输出驱动器，每个子驱动器分支或切片具有显着大于量化步长的标称阻抗，并且通过显着小于量化步长的阻抗步长递增地彼此不同。 在一个实现中，这种“差分”或“不均匀”子驱动器切片实现n选择k均衡器的相应元件，每个这样的差分子驱动器切片由均匀元件阻抗校准DAC实现。 在另一实施方式中，均匀分片均衡器的每个分量由差分片阻抗校准DAC实现，并且在又一实现中，差分片均衡器的每个分量由差分片阻抗校准DAC实现。 在一组额外的实施方案中，均衡和阻抗校准功能在各个并行的驱动器分支组中实现，而不是分层实现中嵌套的“DAC内的DAC”布置。 通过这种双边安排，避免了均衡器和校准器量化的乘法，从而降低了满足指定范围和分辨率所需的副驱动器片的总数。

    High resolution output driver
    4.
    发明授权
    High resolution output driver 有权
    高分辨率输出驱动

    公开(公告)号：US08531206B2

    公开(公告)日：2013-09-10

    申请号：US13391383

    申请日：2010-09-14

    申请人： Amir Amirkhany ,  Chaofeng Huang ,  Kambiz Kaviani ,  Wayne D. Dettloff ,  Kun-Yung Chang

    发明人： Amir Amirkhany ,  Chaofeng Huang ,  Kambiz Kaviani ,  Wayne D. Dettloff ,  Kun-Yung Chang

    IPC分类号： H03K17/16

    CPC分类号： H03K19/0005 ,  H03K19/017581 ,  H03M1/1061 ,  H03M1/745 ,  H04L25/0278 ,  H04L25/0288 ,  H04L25/03343

    摘要： High resolution output drivers having a relatively small number of sub-driver branches or slices each having nominal impedances substantially larger than a quantization step and that incrementally differ from one another by an impedance step substantially smaller than a quantization step. In one implementation, such “differential” or “non-uniform” sub-driver slices implement respective elements of an n choose k equalizer, with each such differential sub-driver slice being implemented by a uniform-element impedance calibration DAC. In another implementation, each component of a uniform-slice equalizer is implemented by a differential-slice impedance calibration DAC, and in yet another implementation, each component of a differential-slice equalizer is implemented by a differential-slice impedance calibration DAC. In an additional set of implementations, equalization and impedance calibration functions are implemented bilaterally in respective parallel sets of driver branches, rather than in the nested “DAC within a DAC” arrangement of the hierarchical implementations. Through such bilateral arrangement, multiplication of the equalizer and calibrator quantizations is avoided, thereby lowering the total number of sub-driver slices required to meet the specified ranges and resolutions.

    摘要翻译： 具有相对较少数量的子驱动器分支或切片的高分辨率输出驱动器，每个子驱动器分支或切片具有显着大于量化步长的标称阻抗，并且通过显着小于量化步长的阻抗步长递增地彼此不同。 在一个实现中，这种“差分”或“不均匀”子驱动器切片实现n选择k均衡器的相应元件，每个这样的差分子驱动器切片由均匀元件阻抗校准DAC实现。 在另一实施方式中，均匀分片均衡器的每个分量由差分片阻抗校准DAC实现，并且在又一实现中，差分片均衡器的每个分量由差分片阻抗校准DAC实现。 在一组额外的实施方案中，均衡和阻抗校准功能在各个并行的驱动器分支组中实现，而不是分层实现中嵌套的“DAC内的DAC”布置。 通过这种双边安排，避免了均衡器和校准器量化的乘法，从而降低了满足指定范围和分辨率所需的副驱动器片的总数。

    Multi-modal communication interface
    5.
    发明授权
    Multi-modal communication interface 有权
    多模态通信接口

    公开(公告)号：US09484891B2

    公开(公告)日：2016-11-01

    申请号：US13880960

    申请日：2012-01-24

    申请人： Amir Amirkhany ,  Chaofeng Huang

    发明人： Amir Amirkhany ,  Chaofeng Huang

    IPC分类号： H03K3/01 ,  H01L27/02 ,  H03K19/003 ,  H03K19/0185

    CPC分类号： H03K3/01 ,  H01L27/0251 ,  H03K19/00315 ,  H03K19/018521 ,  H03K19/018528

    摘要： An integrated circuit supports multiple communication modes using different input/output (IO) voltages. The IC includes a low-voltage communication circuit operating at a low IO voltage in a low-voltage mode, and a high-voltage communication circuit operating at a high IO voltage in a high-voltage mode. The low-voltage communication circuit includes low-voltage transistors in a critical path that exhibits sensitivity to a destructive voltage less than the high IO voltage. The low-voltage communication circuit is therefore provided with protection circuitry to protect the low-voltage transistors from the high 10 voltage.

    摘要翻译： 集成电路支持使用不同输入/输出（IO）电压的多种通信模式。 IC包括在低电压模式下以低IO电压工作的低压通信电路和在高电压模式下以高IO电压工作的高压通信电路。 低压通信电路包括在低于高IO电压的破坏性电压下具有敏感性的关键路径中的低压晶体管。 因此，低压通信电路设置有保护电路以保护低压晶体管免受高10电压的影响。

    Multi-Modal Communication Interface
    6.
    发明申请
    Multi-Modal Communication Interface 有权
    多模态通信接口

    公开(公告)号：US20130278296A1

    公开(公告)日：2013-10-24

    申请号：US13880960

    申请日：2012-01-24

    申请人： Amir Amirkhany ,  Chaofeng Huang

    发明人： Amir Amirkhany ,  Chaofeng Huang

    IPC分类号： H03K3/01

    CPC分类号： H03K3/01 ,  H01L27/0251 ,  H03K19/00315 ,  H03K19/018521 ,  H03K19/018528

    摘要： An integrated circuit supports multiple communication modes using different input/output (IO) voltages. The IC includes a low-voltage communication circuit operating at a low IO voltage in a low-voltage mode, and a high-voltage communication circuit operating at a high IO voltage in a high-voltage mode. The low-voltage communication circuit includes low-voltage transistors in a critical path that exhibits sensitivity to a destructive voltage less than the high IO voltage. The low-voltage communication circuit is therefore provided with protection circuitry to protect the low-voltage transistors from the high 10 voltage.

    摘要翻译： 集成电路支持使用不同输入/输出（IO）电压的多种通信模式。 IC包括在低电压模式下以低IO电压工作的低压通信电路和在高电压模式下以高IO电压工作的高压通信电路。 低压通信电路包括在低于高IO电压的破坏性电压下具有敏感性的关键路径中的低压晶体管。 因此，低压通信电路设置有保护电路以保护低压晶体管免受高10电压的影响。

    Geometric D/A converter for a delay-locked loop
    7.
    发明授权
    Geometric D/A converter for a delay-locked loop 失效
    用于延迟锁定环路的几何D / A转换器

    公开(公告)号：US06975260B1

    公开(公告)日：2005-12-13

    申请号：US10986707

    申请日：2004-11-12

    申请人： Shahram Abdollahi-Alibeik ,  Chaofeng Huang

    发明人： Shahram Abdollahi-Alibeik ,  Chaofeng Huang

    IPC分类号： H03M1/66 ,  H03M1/68 ,  H03M1/74

    CPC分类号： H03M1/68 ,  H03M1/745

    摘要： A geometric DAC architecture includes a series of substantially identical sub-DACs, each sub-DAC having n taps. The sub-DACs are fed from a bias-DAC having m=(total number of taps needed)/n taps. The output of each of the m taps is increased geometrically at a rate of kn. The geometric DAC architecture control lines desirably require only (m+n) taps compared with (m×n) taps for the simpler more conventional approach. Further, the geometric DAC architecture requires less real estate than the simpler more conventional approach, is easy to expand because it is modular, and generates an output current that is always monotonic, regardless of errors in transistor sizes and PVT variations. The n tap control lines are coded by alternately inverting n control line inputs between sub-DACs such that any state transition associated with the geometric DAC occurs with only one bit change in each of the control lines.

    摘要翻译： 几何DAC架构包括一系列基本相同的子DAC，每个子DAC具有n个抽头。 子DAC从具有m =（所需抽头总数）/ n抽头的偏置DAC馈送。 m个抽头中的每一个的输出以几何的方式以k 的速率增加。 对于更简单的更传统的方法，几何DAC架构控制线期望仅需要（m + n）个抽头与（m×n）抽头相比较。 此外，几何DAC架构比简单的更传统的方法需要更少的空间，由于它是模块化而容易扩展，并且产生总是单调的输出电流，而不管晶体管尺寸和PVT变化中的错误。 通过在子DAC之间交替地反转n个控制线输入来编码n个抽头控制线，使得与几何DAC相关联的任何状态转换在每个控制线中仅发生一个位改变。

    Timing synchronization methods and systems for transmit parallel interfaces
    8.
    发明授权
    Timing synchronization methods and systems for transmit parallel interfaces 失效
    用于传输并行接口的定时同步方法和系统

    公开(公告)号：US06977980B2

    公开(公告)日：2005-12-20

    申请号：US09942198

    申请日：2001-08-29

    申请人： Kun-Yung Ken Chang ,  Chaofeng Huang

    发明人： Kun-Yung Ken Chang ,  Chaofeng Huang

    IPC分类号： H04L7/02 ,  H04L7/00

    CPC分类号： H04L7/02

    摘要： Transmit parallel interfaces and methods are provided in which a clock signal is generated that maximizes the setup and hold window of input data. In at least some embodiments, a divider circuit provides a clock signal in one clock domain that has a rising edge located very close to the falling edge of a system clock in another clock domain.

    摘要翻译： 提供了发送并行接口和方法，其中产生使输入数据的建立和保持窗口最大化的时钟信号。 在至少一些实施例中，分频器电路在一个时钟域提供时钟信号，该时钟信号具有非常接近另一个时钟域中系统时钟下降沿的上升沿。

    Apparatus and method for producing dummy data and output clock generator using same
    10.
    发明授权
    Apparatus and method for producing dummy data and output clock generator using same 失效
    用于产生伪数据的装置和方法以及使用其的输出时钟发生器

    公开(公告)号：US07464282B1

    公开(公告)日：2008-12-09

    申请号：US10654322

    申请日：2003-09-03

    申请人： Shahram Abdollahi-Alibeik ,  Chaofeng Huang

    发明人： Shahram Abdollahi-Alibeik ,  Chaofeng Huang

    IPC分类号： G06F1/12

    CPC分类号： G11C7/22 ,  G11C7/222 ,  G11C2207/2254 ,  H03L7/0814

    摘要： An apparatus and method for producing dummy data is based on timing paths co-located with the address/data paths of the memory. An output clock generator uses the dummy data. The technique for producing dummy data is particularly important for memory systems in which the output of memory cells do not normally provide large voltage swings, making them less practical for self timing approaches to dummy data generation.

    摘要翻译： 用于产生伪数据的装置和方法基于与存储器的地址/数据路径共同定位的定时路径。 输出时钟发生器使用虚拟数据。 用于产生虚拟数据的技术对于其中存储器单元的输出通常不提供大的电压摆动的存储器系统是特别重要的，使得它们对于伪数据生成的自定时方法不太实用。