公开(公告)号：US5907462A

公开(公告)日：1999-05-25

申请号：US302145

申请日：1994-09-07

申请人： Amitava Chatterjee ,  Charvaka Duvvury ,  Ping Yang ,  Ekanayake Ajith Amerasekera

发明人： Amitava Chatterjee ,  Charvaka Duvvury ,  Ping Yang ,  Ekanayake Ajith Amerasekera

IPC分类号： H01L27/02 ,  H02H9/00

CPC分类号： H01L27/0262 ,  H01L29/87

摘要： A protection device comprising a gate-coupled silicon-controlled rectifier (SCR) (100), SCR (100) comprises an anode (105) formed in n-well (104) and connected to a pad (128) and a cathode (111) connected to ground. A gate-coupled NMOS transistor (120) has a gate (116) connected through a resistive element (118) to ground. A n+ region (112) forms both the cathode (111) and a source of the NMOS transistor (120). N-well (104) forms the drain. Stress voltage is coupled from pad (128) to gate electrode (116) causing NMOS transistor (120) to conduct. This, in turn, triggers SCR (100) which dissipates the stress current at the pad (128). The coupled voltage at gate electrode (116) dissipates within a designed time constant through resistive element (118).

摘要翻译： 一种保护装置，包括栅极耦合的可硅可控整流器（SCR）（100），SCR（100）包括形成在n阱（104）中并连接到焊盘（128）和阴极（111）的阳极 ）连接到地面。 栅极耦合NMOS晶体管（120）具有通过电阻元件（118）连接到地的栅极（116）。 n +区域（112）形成阴极（111）和NMOS晶体管（120）的源极。 N阱（104）形成排水管。 应力电压从焊盘（128）耦合到栅电极（116），导致NMOS晶体管（120）导通。 这反过来又触发SCR（100），其消耗衬垫（128）处的应力电流。 栅极（116）处的耦合电压通过电阻元件（118）在设计的时间常数内消散。

公开(公告)号：US06125021A

公开(公告)日：2000-09-26

申请号：US841752

申请日：1997-04-30

申请人： Charvaka Duvvury ,  Steven E. Marum ,  Amitava Chatterjee

发明人： Charvaka Duvvury ,  Steven E. Marum ,  Amitava Chatterjee

IPC分类号： H01L27/02 ,  H02H9/04

CPC分类号： H01L27/0251 ,  H01L27/0266

摘要： An integrated circuit (10) with ESD protection is provided. The integrated circuit (10) includes a clamping device (28) connected to an input pad (12) of the integrated circuit and to ground (22). The clamping device (28) limits the peak voltage of an ESD pulse applied to the input pad (12) by conducting it to ground (22). A protection device (16) is connected to an input pad (12) of the integrated circuit (10) and to ground. The protection device (16) discharges the energy of the ESD pulse to ground. The protection device (16) is coordinated with the clamping device (28) such that the clamping device (28) turns on before the protection device (16).

摘要翻译： 提供具有ESD保护的集成电路（10）。 集成电路（10）包括连接到集成电路的输入焊盘（12）并接地（22）的夹持装置（28）。 钳位装置（28）通过将其接地（22）来限制施加到输入焊盘（12）的ESD脉冲的峰值电压。 保护装置（16）连接到集成电路（10）的输入焊盘（12）并接地。 保护装置（16）将ESD脉冲的能量释放到地。 保护装置（16）与夹紧装置（28）协调，使得夹紧装置（28）在保护装置（16）之前打开。

公开(公告)号：US4896243A

公开(公告)日：1990-01-23

申请号：US287427

申请日：1988-12-20

申请人： Amitava Chatterjee ,  Charvaka Duvvury

发明人： Amitava Chatterjee ,  Charvaka Duvvury

IPC分类号： H01L27/02 ,  H01L29/8605

CPC分类号： H01L29/8605 ,  H01L27/0251

摘要： An efficient ESD protection circuit is provided having a resistor (18) disposed between an input pin (12) and the functioning circuitry (22) of an integrated circuit package. A primary switching device (28) is electrically connected between the input pin (12) and a reference voltage pin (14). The resistor (18) comprises an N- well (48) formed within the P- substrate (44) and an N+ diffused reion (50) formed within the N- well (48). A silicided layer (52) is formed over the N+ region (50). The primary switching device (28) is constructed to share the same PN junction (54) utilized by the resistor (18). In constructing the primary switching device (28), a P+ region (70) is formed within the N- well (48). Further, an N+ region (68) is formed within the P- substrate (44). Thus, the primary switching device (40) includes three PN junctions (72, 54, 74) which will conduct at a time prior to, or contemporaneous with, the breakdown of resistor (18).

摘要翻译： 提供了一种高效的ESD保护电路，其具有设置在集成电路封装的输入引脚（12）和功能电路（22）之间的电阻器（18）。 主开关装置（28）电连接在输入引脚（12）和参考电压引脚（14）之间。 电阻器（18）包括形成在P-衬底（44）内的N阱（48）和形成在N阱（48）内的N +扩散的ion（50）。 在N +区域（50）上形成硅化物层（52）。 主开关器件（28）被构造成共享由电阻器（18）使用的相同的PN结（54）。 在构成初级开关器件（28）时，在N阱（48）内形成有P +区（70）。 此外，在P-衬底（44）内形成N +区（68）。 因此，初级开关器件（40）包括三个PN结（72,54,74），其将在电阻器（18）的击穿之前或同时进行的时间传导。

公开(公告)号：US08829618B2

公开(公告)日：2014-09-09

申请号：US13288507

申请日：2011-11-03

申请人： Ponnarith Pok ,  Kyle Schulmeyer ,  Roger A. Cline ,  Charvaka Duvvury

发明人： Ponnarith Pok ,  Kyle Schulmeyer ,  Roger A. Cline ,  Charvaka Duvvury

IPC分类号： H01L21/00 ,  H01L27/02 ,  H01L29/78

CPC分类号： H01L27/0255 ,  H01L21/823481 ,  H01L27/0274 ,  H01L27/0629 ,  H01L29/66136 ,  H01L29/78

摘要： An ESD protection circuit with a diode string coupled to a diode-isolated, gate-grounded NMOS ESD device. A method of forming an ESD protection circuit with a diode string coupled to a diode-isolated, gate-grounded NMOS ESD device.

摘要翻译： 一个ESD保护电路，其二极管串耦合到二极管隔离的栅极接地NMOS ESD器件。 一种形成具有耦合到二极管隔离的栅极接地NMOS ESD器件的二极管串列的ESD保护电路的方法。

公开(公告)号：US07872841B2

公开(公告)日：2011-01-18

申请号：US12049726

申请日：2008-03-17

申请人： Yves Leduc ,  Nathalie Messina ,  Charvaka Duvvury ,  Kurt P. Wachtler

发明人： Yves Leduc ,  Nathalie Messina ,  Charvaka Duvvury ,  Kurt P. Wachtler

IPC分类号： H02H9/00

CPC分类号： H01L23/62 ,  H01L23/60 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/13034 ,  H01L2924/15311 ,  H05K1/0259 ,  H05K2201/0738 ,  Y10T29/49105 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A packaged semiconductor device (200) with a substrate (220) having, sandwiched in an insulator (221), a flat sheet-like sieve member (240) made of a non-linear material switching from insulator to conductor mode at a preset voltage. Both member surfaces are free of indentations; the member is perforated by through-holes, which are grouped into a first set (241) and a second set (242). Metal traces (251) over one member surface are positioned across the first set through-holes (241); each trace is connected to a terminal on the substrate top and, through the hole, to a terminal on the substrate bottom. Analogous for metal traces (252) over the opposite member surface and second set through-holes (242). Traces (252) overlap with a portion of traces (252) to form the locations for the conductivity switches, creating local ultra-low resistance bypasses to ground for discharging overstress events.

摘要翻译： 一种封装半导体器件（200），其具有夹在绝缘体（221）中的基板（220），由预定电压从绝缘体切换到导体模式的非线性材料制成的平板状筛件（240） 。 两个构件表面都没有压痕; 所述构件穿过通孔，所述通孔被分组成第一组（241）和第二组（242）。 一个构件表面上的金属迹线（251）跨过第一组通孔（241）定位; 每个迹线连接到基板顶部上的端子，并且通过孔连接到基板底部上的端子。 类似于相对构件表面上的金属迹线（252）和第二组通孔（242）。 轨迹（252）与轨迹（252）的一部分重叠以形成用于导电开关的位置，从而产生局部超低电阻旁路到地以释放过应力事件。

公开(公告)号：US20070284666A1

公开(公告)日：2007-12-13

申请号：US11739801

申请日：2007-04-25

申请人： Charvaka Duvvury ,  Gianluca Boselli

发明人： Charvaka Duvvury ,  Gianluca Boselli

IPC分类号： H01L29/78

CPC分类号： H01L27/0255 ,  H01L27/0292

摘要： A semiconductor device for locally protecting an integrated circuit input/output (I/O) pad (301) against ESD events, when the I/O pad is located between a power pad (303) and a ground potential pad (305a). A first diode (311) and a second diode (312) are connected in series, the anode (311b) of the series connected to the I/O pad and the cathode (312a) connected to the power pad. A third diode (304) has its anode (304b) tied to the ground pad and its cathode (304a) tied to the I/O pad. A string (320) of at least one diode has its anode (321b) connected to the series between the first and second diode (node 313), isolated from the I/O pad, and its cathode (323a) connected to the ground pad. The string (320) may comprise three or more diodes.

摘要翻译： 当所述I / O焊盘位于电源焊盘（303）和接地电位焊盘（305a）之间时，用于局部保护集成电路输入/输出（I / O）焊盘（301）的ESD事件的半导体器件。 第一二极管（311）和第二二极管（312）串联连接，串联的阳极（311b）连接到连接到电源板的I / O焊盘和阴极（312a）。 第三二极管（304）的阳极（304b）连接到接地焊盘，其阴极（304a）连接到I / O焊盘。 至少一个二极管的串（320）具有连接到与I / O焊盘隔离的第一和第二二极管（节点313）之间的串联的阳极（321b），并且其阳极（323a）连接到 接地垫 串（320）可以包括三个或更多个二极管。

公开(公告)号：US20060050453A1

公开(公告)日：2006-03-09

申请号：US10936912

申请日：2004-09-08

申请人： Charvaka Duvvury ,  Gianluca Boselli

发明人： Charvaka Duvvury ,  Gianluca Boselli

IPC分类号： H02H9/00

CPC分类号： H01L27/0255 ,  H01L27/0292

摘要： A semiconductor device for locally protecting an integrated circuit input/output (I/O) pad (301) against ESD events, when the I/O pad is located between a power pad (303) and a ground potential pad (305a). A first diode (311) and a second diode (312) are connected in series, the anode (311b) of the series connected to the I/O pad and the cathode (312a) connected to the power pad. A third diode (304) has its anode (304b) tied to the ground pad and its cathode (304a) tied to the I/O pad. A string (320) of at least one diode has its anode (321b) connected to the series between the first and second diode (node 313), isolated from the I/O pad, and its cathode (323a) connected to the ground pad. The string (320) may comprise three or more diodes.

摘要翻译： 当所述I / O焊盘位于电源焊盘（303）和接地电位焊盘（305a）之间时，用于局部保护集成电路输入/输出（I / O）焊盘（301）的ESD事件的半导体器件。 第一二极管（311）和第二二极管（312）串联连接，串联的阳极（311b）连接到连接到电源板的I / O焊盘和阴极（312a）。 第三二极管（304）的阳极（304b）连接到接地焊盘，其阴极（304a）连接到I / O焊盘。 至少一个二极管的串（320）具有连接到与I / O焊盘隔离的第一和第二二极管（节点313）之间的串联的阳极（321b），并且其阳极（323a）连接到 接地垫 串（320）可以包括三个或更多个二极管。

公开(公告)号：US06933567B2

公开(公告)日：2005-08-23

申请号：US10146158

申请日：2002-05-15

申请人： Charvaka Duvvury ,  Sridhar Ramaswamy

发明人： Charvaka Duvvury ,  Sridhar Ramaswamy

IPC分类号： H01L23/62 ,  H01L27/02 ,  H01L31/392

CPC分类号： H01L27/0277

摘要： An electrostatic discharge (ESD) protection device formed in the semiconductor layer of a semiconductor-on-insulator device, wherein the semiconductor layer has first and second wells. A discharge circuit is formed in the first well, operable to discharge the ESD pulse to ground. A pump circuit is formed in the second well, operable to use a portion of an ESD pulse's voltage to pump current into the first well for allowing the discharge circuit to turn on uniformly. The discharge circuit has a plurality of body nodes to the first well. The pump circuit comprises an input pad for receiving a portion of the ESD pulse's voltage; an MOS transistor having source, gate and drain; a capacitor connected between the input pad and the gate, whereby a rising input voltage pulls the gate transiently high for pumping current into the first well; the source is connected to the body nodes of the discharge circuit, and the drain connected to the input pad.

摘要翻译： 一种形成在绝缘体上半导体器件的半导体层中的静电放电（ESD）保护器件，其中半导体层具有第一和第二阱。 在第一阱中形成放电电路，用于将ESD脉冲放电到地。 泵电路形成在第二阱中，可操作以使用ESD脉冲的一部分电压将电流泵入第一阱，以允许放电电路均匀地导通。 放电电路具有到第一阱的多个体节点。 泵电路包括用于接收ESD脉冲电压的一部分的输入焊盘; 具有源极，栅极和漏极的MOS晶体管; 连接在输入焊盘和栅极之间的电容器，由此上升的输入电压将栅极瞬时拉高以将电流泵入第一阱; 源极连接到放电电路的主体节点，并且漏极连接到输入焊盘。

公开(公告)号：US06534833B1

公开(公告)日：2003-03-18

申请号：US09040763

申请日：1998-03-18

申请人： Charvaka Duvvury ,  Michael D. Chaine ,  Puvvada Venugopal

发明人： Charvaka Duvvury ,  Michael D. Chaine ,  Puvvada Venugopal

IPC分类号： H01L2972

CPC分类号： H01L27/0266

摘要： The invention comprises a semiconductor device with protection circuitry and a method of protecting an integrated circuit from electrostatic discharge. One aspect of the invention is a semiconductor device with protection circuitry which comprises an integrated circuit having at least one bond pad. A protection circuit is electrically connected to the bond pad and is operable to prevent damage to the integrated circuit during an electrostatic discharge event. The protection circuit comprises a first MOSFET having a first gate electrode connected in series with a second MOSFET having a second gate electrode wherein the first gate electrode and second gate electrode are commonly controlled in response to an electrostatic discharge event.

摘要翻译： 本发明包括具有保护电路的半导体器件和保护集成电路免受静电放电的方法。 本发明的一个方面是具有保护电路的半导体器件，其包括具有至少一个接合焊盘的集成电路。 保护电路电连接到接合焊盘，并且可操作以防止在静电放电事件期间对集成电路的损坏。 保护电路包括第一MOSFET，其具有与具有第二栅电极的第二MOSFET串联连接的第一栅电极，其中第一栅极电极和第二栅极电极响应于静电放电事件共同控制。

公开(公告)号：US6040968A

公开(公告)日：2000-03-21

申请号：US99654

申请日：1998-06-17

申请人： Charvaka Duvvury ,  E. Ajith Amerasekera ,  Sridhar Ramaswamy

发明人： Charvaka Duvvury ,  E. Ajith Amerasekera ,  Sridhar Ramaswamy

IPC分类号： H01L27/02 ,  H02H9/00

CPC分类号： H01L27/0251 ,  H01L27/0248

摘要： A method for achieving improving ESD protection in integrated circuits. Capacitance associated with a power supply plays an important role in ESD protection and increasing Vcc.sub.-- c capacitance by integrating distributed capacitors as junction capacitors, or MOS capacitors along Vcc and grounded n+ diffusion parallel runs improves protection against ESD and EOS. Additionally, at least a pair of antiparallel diodes interposed between the periphery voltage source and internal core circuitry voltage provides an added noise margin.

摘要翻译： 实现集成电路中ESD保护改进的方法。 与电源相关的电容在ESD保护中起着重要作用，通过将分布式电容器集成为结电容器，或沿着Vcc和接地的n +扩散并联运行的MOS电容器提高Vcc-c电容，提高了ESD和EOS的保护。 此外，插入在外围电压源和内部电路电压之间的至少一对反并联二极管提供了增加的噪声容限。