公开(公告)号：US09922919B2

公开(公告)日：2018-03-20

申请号：US14984064

申请日：2015-12-30

申请人： Amkor Technology, Inc.

发明人： Won Bae Bang ,  Byong Jin Kim ,  Gi Jeong Kim ,  Ji Young Chung

IPC分类号： H01L23/495 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/498 ,  H01L21/48 ,  H01L23/31

CPC分类号： H01L23/49827 ,  H01L21/4828 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49861 ,  H01L2224/16225 ,  H01L2924/181 ,  H01L2924/00012

摘要： In one embodiment, an electronic package includes a substrate having a plurality of lands embedded within an insulating layer. Conductive patterns are disposed on at least a portion of a respective land top surface. An electronic device is electrically connected to the conductive patterns and a package body encapsulating the top surface of the insulating material and the electronic device, wherein the bottom land surfaces are exposed to the outside. In another embodiment, the top land surfaces and the top surface of the insulating layer are substantially co-planar and the conductive patterns further overlap portions of the top surface of the insulating layer.

公开(公告)号：US09613829B1

公开(公告)日：2017-04-04

申请号：US15148895

申请日：2016-05-06

申请人： Amkor Technology, Inc.

发明人： Seung Woo Lee ,  Byong Jin Kim ,  Won Bae Bang ,  Sang Goo Kang

IPC分类号： H01L29/84 ,  H01L21/48 ,  H01L23/31 ,  H01L23/495 ,  H01L23/522 ,  H01L21/56

CPC分类号： H01L23/49861 ,  H01L21/4839 ,  H01L21/4853 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3157 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

摘要： Provided are a method for fabricating a semiconductor package and a semiconductor package using the same, which can simplify a fabricating process of the semiconductor package by forming a lead frame on which a semiconductor die can be mounted without a separate grinding process, and can improve product reliability by preventing warpage from occurring during a grinding process. In one embodiment, the method for fabricating a semiconductor package includes forming a frame on a carrier, forming a first pattern layer on the frame, first encapsulating the frame and the first pattern layer using a first encapsulant, forming conductive vias electrically connected to the first pattern layer while passing through the first encapsulant, forming a second pattern layer electrically connected to the conductive vias on the first encapsulant, forming a first solder mask formed on the first encapsulant and exposing a portion of the second pattern layer to the outside, removing the frame by an etching process and etching a portion of the first pattern layer, and attaching a semiconductor die to the first pattern layer.

公开(公告)号：US10910298B2

公开(公告)日：2021-02-02

申请号：US15888003

申请日：2018-02-03

申请人： Amkor Technology, Inc.

发明人： Won Bae Bang ,  Byong Jin Kim ,  Gi Jeong Kim ,  Ji Young Chung

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/495 ,  H01L23/498 ,  H01L23/31

摘要： An electronic package includes a substrate having a plurality of lands embedded within an insulating layer. Conductive patterns are disposed on at least a portion of a respective land top surface. An electronic device is electrically connected to the conductive patterns, wherein the land bottom surfaces are exposed to the outside. In another embodiment, the top land surfaces and the top surface of the insulating layer are substantially co-planar and the conductive patterns further overlap portions of the top surface of the insulating layer. In one embodiment, a package body encapsulates the top surface of the insulating material and the electronic device, wherein the land bottom surfaces are exposed to the outside of the package body.

公开(公告)号：US09978695B1

公开(公告)日：2018-05-22

申请号：US15457937

申请日：2017-03-13

申请人： AMKOR TECHNOLOGY, INC.

发明人： Jae Min Bae ,  Byong Jin Kim ,  Won Bae Bang

IPC分类号： H01L33/62 ,  H01L23/00 ,  H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

CPC分类号： H01L23/564 ,  C08G77/14 ,  C08L83/06 ,  C08L2205/025 ,  E21B21/08 ,  E21B47/101 ,  E21B49/005 ,  G01N29/024 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49548 ,  H01L33/56 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/181 ,  C08L83/00 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： A semiconductor device includes a die pad, a plurality of first lands each having a first land first top recessed portion disposed on a first land first end distal to the die pad, and a plurality of second lands each having a second land first bottom recessed portion disposed on a second land first end distal to the die pad. A semiconductor die is electrically connected to the first and second lands. A package body, which defines a bottom surface and a side surface, at least partially encapsulating the first and second lands and the semiconductor die such that at least portions of the first and second lands are exposed in and substantially flush with the bottom surface of the package body.

公开(公告)号：US20170207162A1

公开(公告)日：2017-07-20

申请号：US15477853

申请日：2017-04-03

申请人： Amkor Technology, Inc.

发明人： Seung Woo Lee ,  Byong Jin Kim ,  Won Bae Bang ,  Sang Goo Kang

IPC分类号： H01L23/498 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L23/49861 ,  H01L21/4839 ,  H01L21/4853 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3157 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

摘要： Provided are a method for fabricating a semiconductor package and a semiconductor package using the same, which can simplify a fabricating process of the semiconductor package by forming a lead frame on which a semiconductor die can be mounted without a separate grinding process, and can improve product reliability by preventing warpage from occurring during a grinding process. In one embodiment, the method for fabricating a semiconductor package includes forming a frame on a carrier, forming a first pattern layer on the frame, first encapsulating the frame and the first pattern layer using a first encapsulant, forming conductive vias electrically connected to the first pattern layer while passing through the first encapsulant, forming a second pattern layer electrically connected to the conductive vias on the first encapsulant, forming a first solder mask formed on the first encapsulant and exposing a portion of the second pattern layer to the outside, removing the frame by an etching process and etching a portion of the first pattern layer, and attaching a semiconductor die to the first pattern layer.

公开(公告)号：US20200273789A1

公开(公告)日：2020-08-27

申请号：US16673032

申请日：2019-11-04

申请人： Amkor Technology, Inc.

发明人： Seung Woo Lee ,  Byong Jin Kim ,  Won Bae Bang ,  Sang Goo Kang

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

摘要： Provided are a method for fabricating a semiconductor package and a semiconductor package using the same, which can simplify a fabricating process of the semiconductor package by forming a lead frame on which a semiconductor die can be mounted without a separate grinding process, and can improve product reliability by preventing warpage from occurring during a grinding process. In one embodiment, the method for fabricating a semiconductor package includes forming a frame on a carrier, forming a first pattern layer on the frame, first encapsulating the frame and the first pattern layer using a first encapsulant, forming conductive vias electrically connected to the first pattern layer while passing through the first encapsulant, forming a second pattern layer electrically connected to the conductive vias on the first encapsulant, forming a first solder mask formed on the first encapsulant and exposing a portion of the second pattern layer to the outside, removing the frame by an etching process and etching a portion of the first pattern layer, and attaching a semiconductor die to the first pattern layer.

公开(公告)号：US10224218B2

公开(公告)日：2019-03-05

申请号：US15173281

申请日：2016-06-03

申请人： Amkor Technology Inc.

发明人： Won Bae Bang ,  Byong Jin Kim ,  Gi Jeong Kim ,  Ji Young Chung

IPC分类号： H01L21/56 ,  H01L21/31 ,  H01L23/498 ,  H01L23/31 ,  H01L21/48

摘要： In one embodiment, a semiconductor package includes a multi-layer encapsulated conductive substrate having a fine pitch. The multi-layer encapsulated conductive substrate includes a conductive leads spaced apart from each other, a first encapsulant disposed between the leads, a first conductive layer electrically connected to the plurality of leads, conductive pillars disposed on the first conductive layer, a second encapsulant encapsulating the first conductive layer and the conductive pillars, and a second conductive layer electrically connected to the conductive pillars and exposed in the second encapsulant. A semiconductor die is electrically connected to the second patterned conductive layer. A third encapsulant covers at least the semiconductor die.

公开(公告)号：US10049954B2

公开(公告)日：2018-08-14

申请号：US15173379

申请日：2016-06-03

申请人： Amkor Technology Inc.

发明人： Won Bae Bang ,  Byong Jin Kim ,  Gi Jeong Kim ,  Jae Doo Kwon ,  Hyung Il Jeon

IPC分类号： H01L23/31 ,  H01L23/498 ,  H01L23/495 ,  H01L23/532 ,  H01L23/00 ,  H01L21/48

摘要： A packaged semiconductor device includes a routable molded lead frame structure with a surface finish layer. In one embodiment, the routable molded lead frame structure includes a first laminated layer including the surface finish layer, vias connected to the surface finish layer, and a first resin layer covering the vias leaving the top surface of the surface finish layer exposed. A second laminated layer includes second conductive patterns connected to the vias, bump pads connected to the second conductive patterns, and a second resin layer covering one side of the first resin layer, the second conductive patterns and the bump pads. A semiconductor die is electrically connected to the surface finish layer and an encapsulant covers the semiconductor die and another side of the first resin layer. The surface finish layer provides a customizable and improved bonding structure for connecting the semiconductor die to the routable molded lead frame structure.

公开(公告)号：US09275939B1

公开(公告)日：2016-03-01

申请号：US14106139

申请日：2013-12-13

申请人： AMKOR TECHNOLOGY, INC.

发明人： Jae Min Bae ,  Byong Jin Kim ,  Won Bae Bang

IPC分类号： H01L23/495 ,  H01L23/00

CPC分类号： H01L23/49541 ,  H01L23/3121 ,  H01L23/4951 ,  H01L23/4952 ,  H01L23/49544 ,  H01L23/49548 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： In one embodiment, a semiconductor device includes a die pad defining multiple peripheral edge segments. In addition, the semiconductor device includes a plurality of leads and lands which are provided in a prescribed arrangement. Connected to the top surface of the die pad is at least one semiconductor die which is electrically connected to at least some of the leads and lands. At least portions of the die pad, the leads, the lands, and the semiconductor die are encapsulated by the package body, with at least portions of the bottom surfaces of the die pad and the lands being exposed in a common exterior surface of the package body.

公开(公告)号：US10468343B2

公开(公告)日：2019-11-05

申请号：US15874602

申请日：2018-01-18

申请人： Amkor Technology, Inc.

发明人： Seung Woo Lee ,  Byong Jin Kim ,  Won Bae Bang ,  Sang Goo Kang

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

摘要： Provided are a method for fabricating a semiconductor package and a semiconductor package using the same, which can simplify a fabricating process of the semiconductor package by forming a lead frame on which a semiconductor die can be mounted without a separate grinding process, and can improve product reliability by preventing warpage from occurring during a grinding process. In one embodiment, the method for fabricating a semiconductor package includes forming a frame on a carrier, forming a first pattern layer on the frame, first encapsulating the frame and the first pattern layer using a first encapsulant, forming conductive vias electrically connected to the first pattern layer while passing through the first encapsulant, forming a second pattern layer electrically connected to the conductive vias on the first encapsulant, forming a first solder mask formed on the first encapsulant and exposing a portion of the second pattern layer to the outside, removing the frame by an etching process and etching a portion of the first pattern layer, and attaching a semiconductor die to the first pattern layer.