公开(公告)号：US10224218B2

公开(公告)日：2019-03-05

申请号：US15173281

申请日：2016-06-03

申请人： Amkor Technology Inc.

发明人： Won Bae Bang ,  Byong Jin Kim ,  Gi Jeong Kim ,  Ji Young Chung

IPC分类号： H01L21/56 ,  H01L21/31 ,  H01L23/498 ,  H01L23/31 ,  H01L21/48

摘要： In one embodiment, a semiconductor package includes a multi-layer encapsulated conductive substrate having a fine pitch. The multi-layer encapsulated conductive substrate includes a conductive leads spaced apart from each other, a first encapsulant disposed between the leads, a first conductive layer electrically connected to the plurality of leads, conductive pillars disposed on the first conductive layer, a second encapsulant encapsulating the first conductive layer and the conductive pillars, and a second conductive layer electrically connected to the conductive pillars and exposed in the second encapsulant. A semiconductor die is electrically connected to the second patterned conductive layer. A third encapsulant covers at least the semiconductor die.

公开(公告)号：US10049954B2

公开(公告)日：2018-08-14

申请号：US15173379

申请日：2016-06-03

申请人： Amkor Technology Inc.

发明人： Won Bae Bang ,  Byong Jin Kim ,  Gi Jeong Kim ,  Jae Doo Kwon ,  Hyung Il Jeon

IPC分类号： H01L23/31 ,  H01L23/498 ,  H01L23/495 ,  H01L23/532 ,  H01L23/00 ,  H01L21/48

摘要： A packaged semiconductor device includes a routable molded lead frame structure with a surface finish layer. In one embodiment, the routable molded lead frame structure includes a first laminated layer including the surface finish layer, vias connected to the surface finish layer, and a first resin layer covering the vias leaving the top surface of the surface finish layer exposed. A second laminated layer includes second conductive patterns connected to the vias, bump pads connected to the second conductive patterns, and a second resin layer covering one side of the first resin layer, the second conductive patterns and the bump pads. A semiconductor die is electrically connected to the surface finish layer and an encapsulant covers the semiconductor die and another side of the first resin layer. The surface finish layer provides a customizable and improved bonding structure for connecting the semiconductor die to the routable molded lead frame structure.

公开(公告)号：US09431334B2

公开(公告)日：2016-08-30

申请号：US14593310

申请日：2015-01-09

申请人： Amkor Technology, Inc.

发明人： Hyung Il Jeon ,  Byong Jin Kim ,  Gi Jeong Kim ,  Jae Min Bae ,  Tae Ki Kim

IPC分类号： H01L23/28 ,  H01L23/498 ,  H01L21/78 ,  H01L21/48 ,  H01L23/31 ,  H01L25/10 ,  H01L25/00 ,  H01L23/00 ,  H01L21/56

CPC分类号： H01L23/49838 ,  H01L21/486 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/81005 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15321 ,  H01L2924/1533 ,  H01L2924/18161 ,  H01L2224/81

摘要： In one embodiment, a semiconductor device includes a single layer substrate having an insulation layer and conductive patterns on a first surface of the insulation layer. A semiconductor die is attached on a first surface of the single layer substrate and electrically connected to the conductive patterns. Conductive bumps are also on the first surface of the single layer substrate and electrically connected to the semiconductor die through the conductive patterns. An encapsulant overlaps at least portions of the first surface of the single layer substrate. The conductive bumps are at least partially exposed in the encapsulant.

摘要翻译： 在一个实施例中，半导体器件包括在绝缘层的第一表面上具有绝缘层和导电图案的单层衬底。 半导体管芯安装在单层衬底的第一表面上并电连接到导电图案。 导电凸块也在单层基板的第一表面上并且通过导电图案电连接到半导体管芯。 密封剂与单层基材的第一表面的至少部分重叠。 导电凸块至少部分地暴露在密封剂中。

公开(公告)号：US10177117B2

公开(公告)日：2019-01-08

申请号：US15133081

申请日：2016-04-19

申请人： Amkor Technology Inc.

发明人： Won Bae Bang ,  Ju Hoon Yoon ,  Ji Young Chung ,  Byong Jin Kim ,  Gi Jeong Kim ,  Choon Heung Lee

IPC分类号： H01L23/538 ,  H01L25/065 ,  H01L23/498 ,  H01L21/48 ,  H01L25/00 ,  H01L23/36 ,  H01L23/31 ,  H01L23/00 ,  H01L23/13

摘要： In one embodiment, a method for fabricating a semiconductor package includes providing a multi-layer molded conductive structure. The multi-layer molded conductive structure includes a first conductive structure disposed on a surface of a carrier and a first encapsulant covering at least portions of the first conductive structure while other portions are exposed in the first encapsulant. A second conductive structure is disposed on the first encapsulant and electrically connected to the first conductive structure. A second encapsulant covers a first portion of the second conductive structure while a second portion of the second conductive structure is exposed to the outside, and a third portion of the second conductive structure is exposed in a receiving space disposed in the second encapsulant. The method includes electrically connecting a semiconductor die to the second conductive structure and in some embodiments removing the carrier.

公开(公告)号：US09552999B2

公开(公告)日：2017-01-24

申请号：US14967293

申请日：2015-12-12

申请人： Amkor Technology, Inc.

发明人： Tae Ki Kim ,  Byong Jin Kim ,  Ji Young Chung ,  Gi Jeong Kim ,  Won Bae Bang

IPC分类号： H01L21/48 ,  H01L23/522 ,  H01L23/495 ,  H01L23/64 ,  H01L23/31 ,  H01L23/66 ,  H01L23/28 ,  H01L21/56

CPC分类号： H01L21/4853 ,  H01L21/4821 ,  H01L21/56 ,  H01L23/28 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49861 ,  H01L23/5227 ,  H01L23/645 ,  H01L23/66 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/131 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/13387 ,  H01L2224/16245 ,  H01L2224/291 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/29387 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/81447 ,  H01L2224/83385 ,  H01L2224/83447 ,  H01L2224/83851 ,  H01L2924/15159 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00012

摘要： In one embodiment, an electronic package includes a substrate having a die pad plurality of lands embedded within substrate encapsulant. An electronic chip including an electronic component is connected to the die pad. The die pad is configured with a recessed well extending from a top surface of the die pad towards a bottom surface of the die pad. The electronic component is position at least proximate to and overlapping the recessed well to increase the distance between the die pad and the electronic component. In one embodiment, the electronic component includes a passive component, such as an inductor. A package body encapsulates the electronic chip and top surfaces of the substrate, and is further disposed within the recessed well. The die pad bottom surface is continuous below the recessed well.

摘要翻译： 在一个实施例中，电子封装包括具有芯片焊盘的衬底，多个焊盘嵌入衬底密封剂内。 包括电子部件的电子芯片连接到管芯焊盘。 管芯焊盘配置有从管芯焊盘的顶表面朝向管芯焊盘的底表面延伸的凹槽。 电子部件至少靠近并与凹槽重叠，以增加管芯焊盘和电子部件之间的距离。 在一个实施例中，电子部件包括无源部件，例如电感器。 封装体封装基片的电子芯片和顶面，并进一步设置在凹槽内。 凹槽垫底表面在凹槽下方连续。

公开(公告)号：US20170005029A1

公开(公告)日：2017-01-05

申请号：US15173281

申请日：2016-06-03

申请人： Amkor Technology Inc.

发明人： Won Bae Bang ,  Byong Jin Kim ,  Gi Jeong Kim ,  Ji Young Chung

IPC分类号： H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

CPC分类号： H01L21/565 ,  H01L21/4857 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49861 ,  H01L2224/16 ,  H01L2924/181 ,  H01L2924/00012

摘要： In one embodiment, a semiconductor package includes a multi-layer encapsulated conductive substrate having a fine pitch. The multi-layer encapsulated conductive substrate includes a conductive leads spaced apart from each other, a first encapsulant disposed between the leads, a first conductive layer electrically connected to the plurality of leads, conductive pillars disposed on the first conductive layer, a second encapsulant encapsulating the first conductive layer and the conductive pillars, and a second conductive layer electrically connected to the conductive pillars and exposed in the second encapsulant. A semiconductor die is electrically connected to the second patterned conductive layer. A third encapsulant covers at least the semiconductor die.

摘要翻译： 在一个实施例中，半导体封装包括具有细间距的多层封装导电衬底。 多层封装导电基板包括彼此间隔开的导电引线，设置在引线之间的第一密封剂，与多个引线电连接的第一导电层，设置在第一导电层上的导电柱，第二密封剂封装 第一导电层和导电柱，以及与导电柱电连接并暴露在第二密封剂中的第二导电层。 半导体管芯电连接到第二图案化导电层。 第三密封剂至少覆盖半导体管芯。

公开(公告)号：US20160225687A1

公开(公告)日：2016-08-04

申请号：US14967293

申请日：2015-12-12

申请人： Amkor Technology, Inc.

发明人： Tae Ki Kim ,  Byong Jin Kim ,  Ji Young Chung ,  Gi Jeong Kim ,  Won Bae Bang

IPC分类号： H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L23/522

CPC分类号： H01L21/4853 ,  H01L21/4821 ,  H01L21/56 ,  H01L23/28 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49861 ,  H01L23/5227 ,  H01L23/645 ,  H01L23/66 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/131 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/13387 ,  H01L2224/16245 ,  H01L2224/291 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/29387 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/81447 ,  H01L2224/83385 ,  H01L2224/83447 ,  H01L2224/83851 ,  H01L2924/15159 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00012

摘要： In one embodiment, an electronic package includes a substrate having a die pad plurality of lands embedded within substrate encapsulant. An electronic chip including an electronic component is connected to the die pad. The die pad is configured with a recessed well extending from a top surface of the die pad towards a bottom surface of the die pad. The electronic component is position at least proximate to and overlapping the recessed well to increase the distance between the die pad and the electronic component. In one embodiment, the electronic component includes a passive component, such as an inductor. A package body encapsulates the electronic chip and top surfaces of the substrate, and is further disposed within the recessed well. The die pad bottom surface is continuous below the recessed well.

摘要翻译： 在一个实施例中，电子封装包括具有芯片焊盘的衬底，多个焊盘嵌入衬底密封剂内。 包括电子部件的电子芯片连接到管芯焊盘。 管芯焊盘配置有从管芯焊盘的顶表面朝向管芯焊盘的底表面延伸的凹槽。 电子部件至少靠近并与凹槽重叠，以增加管芯焊盘和电子部件之间的距离。 在一个实施例中，电子部件包括无源部件，例如电感器。 封装体封装基片的电子芯片和顶表面，并进一步设置在凹槽内。 凹槽垫底表面在凹槽下方连续。

公开(公告)号：US11011455B2

公开(公告)日：2021-05-18

申请号：US15893591

申请日：2018-02-10

申请人： Amkor Technology, Inc.

发明人： Tae Kyung Hwang ,  Eun Sook Sohn ,  Won Joon Kang ,  Gi Jeong Kim

IPC分类号： H01L23/495 ,  H01L23/498 ,  H01L23/31

摘要： A method for providing an electronic package structure includes providing a substrate having a die pad having a die pad top surface and an opposing die pad bottom surface, leads laterally spaced apart from the die pad, and a substrate encapsulant interposed between the die pad and the leads and includes a substrate top surface and an opposing substrate bottom surface. The substrate encapsulant is provided such that the die pad and the leads protrude outward from the substrate bottom surface. The method includes providing an electronic device having opposing major surfaces and a pair of opposing outer edges. The method includes connecting the electronic device to the substrate such that one major surface of the electronic device is spaced apart from the die pad top surface and upper surfaces of the leads, and the outer edges overlap an opposing pair of the leads.

公开(公告)号：US09966652B2

公开(公告)日：2018-05-08

申请号：US14931750

申请日：2015-11-03

申请人： Amkor Technology, Inc.

发明人： Marc Alan Mangrum ,  Hyung Jun Cho ,  Byong Jin Kim ,  Gi Jeong Kim ,  Jae Min Bae ,  Seung Mo Kim ,  Young Ju Lee

IPC分类号： H01Q1/50 ,  H01Q1/22 ,  H01Q9/04

CPC分类号： H01Q1/2283 ,  H01L2223/6677 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/19107 ,  H01Q9/0407 ,  H01L2924/00012 ,  H01L2924/00

摘要： A packaged electronic device includes an integrated antenna as part of a conductive leadframe. The conductive leadframe includes a die paddle have an elongated conductive beam structure configured as a transmission line, and a ground plane structure disposed surrounding the die paddle. The ground plane includes a gap where the transmission line extends to an edge of the packaged electronic device. In one embodiment, selected leads within the leadframe are configured with conductive connective structures as ground pins, source pins, and/or wave guides. In an alternate embodiment, a portion of the integrated antenna is embedded and partially exposed within the body of the packaged electronic device.

公开(公告)号：US09922919B2

公开(公告)日：2018-03-20

申请号：US14984064

申请日：2015-12-30

申请人： Amkor Technology, Inc.

发明人： Won Bae Bang ,  Byong Jin Kim ,  Gi Jeong Kim ,  Ji Young Chung

IPC分类号： H01L23/495 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/498 ,  H01L21/48 ,  H01L23/31

CPC分类号： H01L23/49827 ,  H01L21/4828 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49861 ,  H01L2224/16225 ,  H01L2924/181 ,  H01L2924/00012

摘要： In one embodiment, an electronic package includes a substrate having a plurality of lands embedded within an insulating layer. Conductive patterns are disposed on at least a portion of a respective land top surface. An electronic device is electrically connected to the conductive patterns and a package body encapsulating the top surface of the insulating material and the electronic device, wherein the bottom land surfaces are exposed to the outside. In another embodiment, the top land surfaces and the top surface of the insulating layer are substantially co-planar and the conductive patterns further overlap portions of the top surface of the insulating layer.