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    Semiconductor device having localized extremely thin silicon on insulator channel region
    1.
    发明申请
    Semiconductor device having localized extremely thin silicon on insulator channel region 有权
    半导体器件具有局部极薄的绝缘体上硅沟道区域

    公开(公告)号：US20120104498A1

    公开(公告)日：2012-05-03

    申请号：US12912897

    申请日：2010-10-27

    申请人： Amlan Majumdar ,  Robert J. Miller ,  Muralidhar Ramachandran

    发明人： Amlan Majumdar ,  Robert J. Miller ,  Muralidhar Ramachandran

    IPC分类号： H01L27/12 ,  H01L21/84

    CPC分类号： H01L29/66545 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78654

    摘要： A method of forming a transistor device includes forming a dummy gate stack structure over an SOI starting substrate, comprising a bulk layer, a global BOX layer over the bulk layer, and an SOI layer over the global BOX layer. Self-aligned trenches are formed completely through portions of the SOI layer and the global BOX layer at source and drain regions. Silicon is epitaxially regrown in the source and drain regions, with a local BOX layer re-established in the epitaxially regrown silicon, adjacent to the global BOX layer. A top surface of the local BOX layer is below a top surface of the global BOX layer. Embedded source and drain stressors are formed in the source and drain regions, adjacent a channel region. Silicide contacts are formed on the source and drain regions. The dummy gate stack structure is removed, and a final gate stack structure is formed.

    摘要翻译： 一种形成晶体管器件的方法包括：在SOI起始衬底上形成虚拟栅极堆叠结构，其包括体层，体层上的全局BOX层以及全局BOX层上的SOI层。 自对准沟槽通过SOI层和源极和漏极区域的全局BOX层的部分完全形成。 硅在源极和漏极区域中外延再生长，在外延重新生长的硅中重新建立局部BOX层，邻近全局BOX层。 本地BOX层的顶表面位于全局BOX层的顶表面之下。 在源极和漏极区域中形成嵌入的源极和漏极应力源，邻近沟道区域。 在源极和漏极区域上形成硅化物接触。 去除虚拟栅极堆叠结构，形成最终的栅极堆叠结构。

    Semiconductor device having localized extremely thin silicon on insulator channel region
    2.
    发明授权
    Semiconductor device having localized extremely thin silicon on insulator channel region 有权
    半导体器件具有局部极薄的绝缘体上硅沟道区域

    公开(公告)号：US08685847B2

    公开(公告)日：2014-04-01

    申请号：US12912897

    申请日：2010-10-27

    申请人： Amlan Majumdar ,  Robert J. Miller ,  Muralidhar Ramachandran

    发明人： Amlan Majumdar ,  Robert J. Miller ,  Muralidhar Ramachandran

    IPC分类号： H01L21/425

    CPC分类号： H01L29/66545 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78654

    摘要： A method of forming a transistor device includes forming a dummy gate stack structure over an SOI starting substrate, comprising a bulk layer, a global BOX layer over the bulk layer, and an SOI layer over the global BOX layer. Self-aligned trenches are formed completely through portions of the SOI layer and the global BOX layer at source and drain regions. Silicon is epitaxially regrown in the source and drain regions, with a local BOX layer re-established in the epitaxially regrown silicon, adjacent to the global BOX layer. A top surface of the local BOX layer is below a top surface of the global BOX layer. Embedded source and drain stressors are formed in the source and drain regions, adjacent a channel region. Silicide contacts are formed on the source and drain regions. The dummy gate stack structure is removed, and a final gate stack structure is formed.

    摘要翻译： 一种形成晶体管器件的方法包括：在SOI起始衬底上形成虚拟栅极堆叠结构，其包括体层，体层上的全局BOX层以及全局BOX层上的SOI层。 自对准沟槽通过SOI层和源极和漏极区域的全局BOX层的部分完全形成。 硅在源极和漏极区域中外延再生长，在外延重新生长的硅中重新建立局部BOX层，邻近全局BOX层。 本地BOX层的顶表面位于全局BOX层的顶表面之下。 在源极和漏极区域中形成嵌入的源极和漏极应力源，邻近沟道区域。 在源极和漏极区域上形成硅化物接触。 去除虚拟栅极堆叠结构，形成最终的栅极堆叠结构。

    Fabrication of a vertical heterojunction tunnel-FET
    4.
    发明授权
    Fabrication of a vertical heterojunction tunnel-FET 有权
    垂直异质结隧道FET的制造

    公开(公告)号：US08796735B2

    公开(公告)日：2014-08-05

    申请号：US13430041

    申请日：2012-03-26

    申请人： Isaac Lauer ,  Amlan Majumdar ,  Paul M. Solomon ,  Steven J. Koester

    发明人： Isaac Lauer ,  Amlan Majumdar ,  Paul M. Solomon ,  Steven J. Koester

    IPC分类号： H01L29/66 ,  H01L21/336 ,  H01L29/165 ,  H01L29/739

    CPC分类号： H01L29/165 ,  H01L29/7391

    摘要： Exemplary embodiments include a method for fabricating a heterojunction tunnel field-effect-transistor (FET), the method including forming a gate region on a silicon layer of a silicon-on-insulator (SOI) substrate, forming a drain region on the silicon layer adjacent the gate region and forming a vertical heterojunction source region adjacent the gate region, wherein the vertical heterojunction source region generates a tunnel path inline with a gate field associated with the gate region.

    摘要翻译： 示例性实施例包括用于制造异质结隧道场效应晶体管（FET）的方法，所述方法包括在绝缘体上硅（SOI）衬底的硅层上形成栅区，在硅层上形成漏极区 邻近所述栅极区域并形成与所述栅极区域相邻的垂直异质结源区域，其中所述垂直异质结源区域产生与所述栅极区域相关联的栅极场列的隧道路径。

    NARROW BODY FIELD-EFFECT TRANSISTOR STRUCTURES WITH FREE-STANDING EXTENSION REGIONS
    6.
    发明申请
    NARROW BODY FIELD-EFFECT TRANSISTOR STRUCTURES WITH FREE-STANDING EXTENSION REGIONS 有权
    具有自由扩展区域的窄体现场效应晶体管结构

    公开(公告)号：US20130285142A1

    公开(公告)日：2013-10-31

    申请号：US13457748

    申请日：2012-04-27

    申请人： Josephine B. Chang ,  Michael A. Guillorn ,  Amlan Majumdar ,  Lidija Sekaric

    发明人： Josephine B. Chang ,  Michael A. Guillorn ,  Amlan Majumdar ,  Lidija Sekaric

    IPC分类号： H01L27/12 ,  H01L21/336

    CPC分类号： H01L29/66772 ,  H01L29/785 ,  H01L29/78654

    摘要： Narrow-body FETs, such as, FinFETs and trigates, exhibit superior short-channel characteristics compared to thick-body devices, such as planar bulk Si FETs and planar partially-depleted SOI (PDSOI) FETs. A common problem, however, with narrow-body devices is high series resistance that often negates the short-channel benefits. The high series resistance is due to either dopant pile-up at the SOI/BOX interface or dopant diffusion into the BOX. This disclosure describes a novel narrow-body device geometry that is expected to overcome the high series resistance problem.

    摘要翻译： 窄体FET，例如FinFET和触发器，与诸如平面体SiFET和平面部分耗尽SOI（PDSOI）FET的厚体器件相比，表现出优异的短沟道特性。 然而，窄体设备的一个常见问题是高串联电阻，通常会抵消短通道的好处。 高串联电阻是由于在SOI / BOX界面处的掺杂剂堆积或掺入到BOX中的掺杂物。 本公开描述了一种新颖的窄体装置几何形状，其预期将克服高串联电阻问题。

    Method for fabricating super-steep retrograde well MOSFET on SOI or bulk silicon substrate, and device fabricated in accordance with the method
    7.
    发明授权
    Method for fabricating super-steep retrograde well MOSFET on SOI or bulk silicon substrate, and device fabricated in accordance with the method 有权
    在SOI或体硅衬底上制造超陡逆行阱MOSFET的方法，以及根据该方法制造的器件

    公开(公告)号：US08329564B2

    公开(公告)日：2012-12-11

    申请号：US11925069

    申请日：2007-10-26

    申请人： Jin Cai ,  Amlan Majumdar ,  Tak H. Ning ,  Zhibin Ren

    发明人： Jin Cai ,  Amlan Majumdar ,  Tak H. Ning ,  Zhibin Ren

    IPC分类号： H01L21/20

    CPC分类号： H01L29/1083 ,  H01L21/28052 ,  H01L21/28088 ,  H01L21/28247 ,  H01L29/165 ,  H01L29/4933 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

    摘要： A method is provided to fabricate a semiconductor device, where the method includes providing a substrate comprised of crystalline silicon; implanting a ground plane in the crystalline silicon so as to be adjacent to a surface of the substrate, the ground plane being implanted to exhibit a desired super-steep retrograde well (SSRW) implant doping profile; annealing implant damage using a substantially diffusionless thermal annealing to maintain the desired super-steep retrograde well implant doping profile in the crystalline silicon and, prior to performing a shallow trench isolation process, depositing a silicon cap layer over the surface of the substrate. The substrate may be a bulk Si substrate or a Si-on-insulator substrate. The method accommodates the use of an oxynitride gate stack structure or a high dielectric constant oxide/metal (high-K/metal) gate stack structure. The various thermal processes used during fabrication are selected/controlled so as to maintain the desired super-steep retrograde well implant doping profile in the crystalline silicon.

    摘要翻译： 提供了一种制造半导体器件的方法，其中该方法包括提供由晶体硅构成的衬底; 在晶体硅中注入接地平面以与衬底的表面相邻，所述接地平面被植入以呈现期望的超陡逆向阱（SSRW）注入掺杂分布; 使用基本上无扩散的热退火来退火植入物损伤，以在晶体硅中保持期望的超陡逆向阱注入掺杂分布，并且在执行浅沟槽隔离工艺之前，在衬底的表面上沉积硅帽层。 衬底可以是体积Si衬底或绝缘体上硅衬底。 该方法适应于使用氧氮化物栅叠层结构或高介电常数氧化物/金属（高K /金属）栅叠层结构。 选择/控制在制造期间使用的各种热处理，以便在晶体硅中保持期望的超陡逆向阱注入掺杂分布。

    Replacement spacer for tunnel FETs
    9.
    发明授权
    Replacement spacer for tunnel FETs 有权
    隧道FET替代间隔件

    公开(公告)号：US08178400B2

    公开(公告)日：2012-05-15

    申请号：US12567963

    申请日：2009-09-28

    申请人： Josephine B. Chang ,  Michael A. Guillorn ,  Isaac Lauer ,  Amlan Majumdar

    发明人： Josephine B. Chang ,  Michael A. Guillorn ,  Isaac Lauer ,  Amlan Majumdar

    IPC分类号： H01L21/336 ,  H01L21/8234

    CPC分类号： H01L29/7391 ,  H01L29/66356

    摘要： A semiconductor fabrication method includes depositing a dummy gate layer onto a substrate, patterning the dummy gate layer, depositing a hardmask layer over the dummy gate layer, patterning the hardmask layer, etching a recess into the substrate, adjacent the dummy gate layer, depositing a semiconductor material into the recess, removing the hardmask layer, depositing replacement spacers onto the dummy gate layer, performing an oxide deposition over the dummy gate layer and replacement spacers, removing the dummy gate and replacement spacers, thereby forming a gate recess in the oxide and depositing a gate stack into the recess.

    摘要翻译： 一种半导体制造方法，包括在基板上沉积虚拟栅极层，图案化虚拟栅极层，在伪栅极层上沉积硬掩模层，图案化硬掩模层，在凹模栅极层附近蚀刻到衬底中的凹陷， 将半导体材料进入凹部，去除硬掩模层，将替代间隔物沉积到伪栅极层上，在伪栅极层和替换间隔物上进行氧化物沉积，去除伪栅极和替换间隔物，从而在氧化物中形成栅极凹槽， 将栅极堆叠沉积到凹槽中。

    LOW COST FABRICATION OF DOUBLE BOX BACK GATE SILICON-ON-INSULATOR WAFERS WITH SUBSEQUENT SELF ALIGNED SHALLOW TRENCH ISOLATION
    10.
    发明申请
    LOW COST FABRICATION OF DOUBLE BOX BACK GATE SILICON-ON-INSULATOR WAFERS WITH SUBSEQUENT SELF ALIGNED SHALLOW TRENCH ISOLATION 有权
    具有后续自对准的双盒式背盖的低成本制造硅绝缘体波纹

    公开(公告)号：US20120112309A1

    公开(公告)日：2012-05-10

    申请号：US13350889

    申请日：2012-01-16

    申请人： Robert H. Dennard ,  David R. Greenberg ,  Amlan Majumdar ,  Leathen Shi ,  Jeng-Bang Yau

    发明人： Robert H. Dennard ,  David R. Greenberg ,  Amlan Majumdar ,  Leathen Shi ,  Jeng-Bang Yau

    IPC分类号： H01L27/12 ,  H01L21/762

    CPC分类号： H01L21/84 ,  H01L21/76254 ,  H01L21/76275 ,  H01L21/76283 ,  H01L27/1203

    摘要： A semiconductor substrate structure for manufacturing integrated circuit devices includes a bulk substrate; a lower insulating layer formed on the bulk substrate, the lower insulating layer formed from a pair of separate insulation layers having a bonding interface therebetween; an electrically conductive layer formed on the lower insulating layer; an insulator with etch stop characteristics formed on the electrically conductive layer; an upper insulating layer formed on the etch stop layer; and a semiconductor layer formed on the upper insulating layer. A scheme of subsequently building a dual-depth shallow trench isolation with the deeper STI in the back gate layer self-aligned to the shallower STI in the active region in such a semiconductor substrate is also disclosed.

    摘要翻译： 用于制造集成电路器件的半导体衬底结构包括块状衬底; 形成在所述本体基板上的下绝缘层，所述下绝缘层由一对具有接合界面的分离的绝缘层形成; 形成在下绝缘层上的导电层; 在所述导电层上形成具有蚀刻停止特性的绝缘体; 形成在所述蚀刻停止层上的上绝缘层; 以及形成在上绝缘层上的半导体层。 还公开了一种随后构建双深度浅沟槽隔离的方案，其中在与这种半导体衬底中的有源区域中较浅的STI自对准的背栅层中的较深STI相比较。