公开(公告)号：US09356011B2

公开(公告)日：2016-05-31

申请号：US14446205

申请日：2014-07-29

Applicant: Analog Devices, Inc.

Inventor： David J. Clarke ,  Javier Alejandro Salcedo ,  Brian B. Moane ,  Juan Luo ,  Seamus Murnane ,  Kieran K. Heffernan ,  John Twomey ,  Stephen Denis Heffernan ,  Gavin Patrick Cosgrave

IPC: H01L29/747 ,  H01L27/02 ,  H01L29/66 ,  H01L29/06 ,  H01L27/06 ,  H01L29/74

CPC classification number: H01L27/0248 ,  H01L27/0635 ,  H01L27/0647 ,  H01L29/0692 ,  H01L29/66386 ,  H01L29/7412 ,  H01L29/747

Abstract: Junction-isolated blocking voltage devices and methods of forming the same are provided. In certain implementations, a blocking voltage device includes an anode terminal electrically connected to a first p-well, a cathode terminal electrically connected to a first n-well, a ground terminal electrically connected to a second p-well, and an n-type isolation layer for isolating the first p-well from a p-type substrate. The first p-well and the first n-well operate as a blocking diode. The blocking voltage device further includes a PNPN silicon controlled rectifier (SCR) associated with a P+ region formed in the first n-well, the first n-well, the first p-well, and an N+ region formed in the first p-well. Additionally, the blocking voltage device further includes an NPNPN bidirectional SCR associated with an N+ region formed in the first p-well, the first p-well, the n-type isolation layer, the second p-well, and an N+ region formed in the second p-well.

Abstract translation: 提供了隔离隔离电压装置及其形成方法。 在某些实施方案中，阻断电压装置包括电连接到第一p阱的阳极端子，电连接到第一n阱的阴极端子，电连接到第二p阱的接地端子，以及n型 用于将第一p阱与p型衬底隔离的隔离层。 第一个p阱和第一个n阱作为阻塞二极管工作。 阻断电压装置还包括与形成在第一n阱，第一n阱，第一p阱以及形成在第一p阱中的N +区相关的PN +可控硅整流器（SCR） 。 另外，阻断电压装置还包括与形成在第一p阱，第一p阱，n型隔离层，第二p阱以及形成在第一p阱中的N +区域相关联的N +区域的NPNPN双向SCR 第二个p井。

公开(公告)号：US10043792B2

公开(公告)日：2018-08-07

申请号：US15346527

申请日：2016-11-08

Applicant: ANALOG DEVICES, INC.

Inventor： Edward John Coyne ,  Patrick Martin McGuinness ,  Paul Malachy Daly ,  Bernard Patrick Stenson ,  David J. Clarke ,  Andrew David Bain ,  William Allan Lane

IPC: H01L21/331 ,  H01L23/60 ,  H01L27/02 ,  H01L29/66 ,  H01L29/735 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40

Abstract: An apparatus including an electrostatic discharge (ESD) protection device comprising a semiconductor having first, second and third regions arranged to form a transistor, wherein the first region is doped with a first impurity of a first conductivity type and is separated from the second region which is doped with a second impurity of a second conductivity type opposite the first type, and wherein a dimensional constraint of the regions defines an operational threshold of the ESD protection device. In one example, the separation between a collector and an emitter of a bipolar transistor defines a trigger voltage to cause the electrostatic discharge protection device to become conducting. In another example, a width of a bipolar transistor base controls a holding voltage of the electrostatic discharge protection device.

公开(公告)号：US20170117266A1

公开(公告)日：2017-04-27

申请号：US15346527

申请日：2016-11-08

Applicant: ANALOG DEVICES, INC.

Inventor： Edward John Coyne ,  Patrick Martin McGuinness ,  Paul Malachy Daly ,  Bernard Patrick Stenson ,  David J. Clarke ,  Andrew David Bain ,  William Allan Lane

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/08 ,  H01L29/40 ,  H01L29/735 ,  H01L29/06

CPC classification number: H01L27/0259 ,  H01L29/0692 ,  H01L29/0821 ,  H01L29/36 ,  H01L29/402 ,  H01L29/6625 ,  H01L29/735 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An apparatus including an electrostatic discharge (ESD) protection device comprising a semiconductor having first, second and third regions arranged to form a transistor, wherein the first region is doped with a first impurity of a first conductivity type and is separated from the second region which is doped with a second impurity of a second conductivity type opposite the first type, and wherein a dimensional constraint of the regions defines an operational threshold of the ESD protection device. In one example, the separation between a collector and an emitter of a bipolar transistor defines a trigger voltage to cause the electrostatic discharge protection device to become conducting. In another example, a width of a bipolar transistor base controls a holding voltage of the electrostatic discharge protection device.

公开(公告)号：US20140332843A1

公开(公告)日：2014-11-13

申请号：US14446205

申请日：2014-07-29

Applicant: Analog Devices, Inc.

Inventor： David J. Clarke ,  Javier Alejandro Salcedo ,  Brian B. Moane ,  Juan Luo ,  Seamus Murnane ,  Kieran K. Heffernan ,  John Twomey ,  Stephen Denis Heffernan ,  Gavin Patrick Cosgrave

IPC: H01L27/02 ,  H01L29/747 ,  H01L29/74 ,  H01L27/06

CPC classification number: H01L27/0248 ,  H01L27/0635 ,  H01L27/0647 ,  H01L29/0692 ,  H01L29/66386 ,  H01L29/7412 ,  H01L29/747

Abstract: Junction-isolated blocking voltage devices and methods of forming the same are provided. In certain implementations, a blocking voltage device includes an anode terminal electrically connected to a first p-well, a cathode terminal electrically connected to a first n-well, a ground terminal electrically connected to a second p-well, and an n-type isolation layer for isolating the first p-well from a p-type substrate. The first p-well and the first n-well operate as a blocking diode. The blocking voltage device further includes a PNPN silicon controlled rectifier (SCR) associated with a P+ region formed in the first n-well, the first n-well, the first p-well, and an N+ region formed in the first p-well. Additionally, the blocking voltage device further includes an NPNPN bidirectional SCR associated with an N+ region formed in the first p-well, the first p-well, the n-type isolation layer, the second p-well, and an N+ region formed in the second p-well.

Abstract translation: 提供了隔离隔离电压装置及其形成方法。 在某些实施方案中，阻断电压装置包括电连接到第一p阱的阳极端子，电连接到第一n阱的阴极端子，电连接到第二p阱的接地端子，以及n型 用于将第一p阱与p型衬底隔离的隔离层。 第一个p阱和第一个n阱作为阻塞二极管工作。 阻断电压装置还包括与形成在第一n阱，第一n阱，第一p阱以及形成在第一p阱中的N +区相关的PN +可控硅整流器（SCR） 。 另外，阻断电压装置还包括与形成在第一p阱，第一p阱，n型隔离层，第二p阱以及形成在第一p阱中的N +区域相关联的N +区域的NPNPN双向SCR 第二个p井。