公开(公告)号：US5899706A

公开(公告)日：1999-05-04

申请号：US884862

申请日：1997-06-30

申请人： Andreas Kluwe ,  Lars Liebmann ,  Frank Prein ,  Thomas Zell

发明人： Andreas Kluwe ,  Lars Liebmann ,  Frank Prein ,  Thomas Zell

IPC分类号： H01L21/82 ,  H01L21/8242 ,  H01L23/528 ,  H01L27/108

CPC分类号： H01L23/528 ,  H01L2924/0002 ,  Y10S438/926

摘要： In preparation for etch processing a semiconductor chip having areas of little or no pattern and areas that are heavily patterned, adding non-operative patterns to the areas having little or no pattern so that the overall pattern density is about the same across the chip.

摘要翻译： 为了准备蚀刻处理，具有很少或没有图案的区域的半导体芯片和大量图案的区域，将非操作图案添加到具有很少或没有图案的区域，使得整个图案密度在整个芯片上大致相同。

公开(公告)号：US6103592A

公开(公告)日：2000-08-15

申请号：US850093

申请日：1997-05-01

申请人： Max Gerald Levy ,  Bernhard Fiegl ,  Walter Glashauser ,  Frank Prein

发明人： Max Gerald Levy ,  Bernhard Fiegl ,  Walter Glashauser ,  Frank Prein

IPC分类号： H01L21/76 ,  H01L21/304 ,  H01L21/306 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108

CPC分类号： H01L21/76229

摘要： FET devices are manufactured using STI on a semiconductor substrate coated with a pad from which are formed raised active silicon device areas and dummy active silicon mesas capped with pad structures on the doped silicon substrate and pad structure. A conformal blanket silicon oxide layer is deposited on the device with conformal projections above the mesas. Then a polysilicon film on the blanket silicon oxide layer is deposited with conformal projections above the mesas. The polysilicon film projections are removed in a CMP polishing step which continues until the silicon oxide layer is exposed over the pad structures. Selective RIE partial etching of the conformal silicon oxide layer over the mesas is next, followed in turn by CMP planarization of the conformal blanket silicon oxide layer which converts the silicon oxide layer into a planar silicon oxide layer, using the pad silicon nitride as an etch stop.

摘要翻译： 在装有衬垫的半导体衬底上使用STI制造FET器件，在衬底上形成凸起的有源硅器件区域，并且在掺杂硅衬底和衬垫结构上形成有衬垫结构的虚拟活性硅台面。 保形层氧化硅层沉积在具有在台面上方的共形突起的器件上。 然后在覆层氧化硅层上沉积具有在台面上方的共形突起的多晶硅膜。 在CMP抛光步骤中去除多晶硅膜突起，其继续直到氧化硅层暴露在焊盘结构上。 接下来，在台面上的适形氧化硅层的选择性RIE局部蚀刻，接着是通过使用衬垫氮化硅作为蚀刻将氧化硅层转换成平面氧化硅层的共形覆盖层氧化硅层的CMP平坦化 停止。

公开(公告)号：US6136677A

公开(公告)日：2000-10-24

申请号：US937781

申请日：1997-09-25

申请人： Frank Prein

发明人： Frank Prein

IPC分类号： H01L21/28 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8239 ,  H01L27/04 ,  H01L27/088 ,  H01L27/105 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/44 ,  H01L21/4763

CPC分类号： H01L27/1052 ,  H01L27/105

摘要： A method of fabricating a semiconductor device includes the steps of providing a semiconductor chip (10) with a memory area (22) and a logic area (26). The memory area (22) and the logic area (26) each have gate structures (50) formed therein. The step of sequentially forming silicided junctions (44) in the logic area (26) and implanted junctions in the memory area (26) is also included.

摘要翻译： 制造半导体器件的方法包括以下步骤：提供具有存储区域（22）和逻辑区域（26）的半导体芯片（10）。 存储区域（22）和逻辑区域（26）各形成有门结构（50）。 还包括在逻辑区域（26）中依次形成硅化物结（44）和在存储区域（26）中植入的结点的步骤。

公开(公告)号：US5608257A

公开(公告)日：1997-03-04

申请号：US477060

申请日：1995-06-07

申请人： Pei-Ing P. Lee ,  Frank Prein

发明人： Pei-Ing P. Lee ,  Frank Prein

IPC分类号： B23K26/00 ,  H01L21/302 ,  H01L21/461 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8242 ,  H01L23/525 ,  H01L27/04 ,  H01L27/108 ,  H01L27/10 ,  H01L29/00

CPC分类号： H01L23/5258 ,  H01L2924/0002

摘要： In an integrated circuit having interconnecting lines formed on an insulated layer deposited on a semiconductor substrate which provide connections between elements integral to the integrated circuit, a fuse structure programmable by a laser beam that includes: a melt-away elongated fuse link joining two segments of an interconnecting line; a plurality of fins integral and coplanar to the fuse link, each of the fins transversally extending away from the fuse link for absorbing energy emitted by the laser beam; and a reflecting plate positioned underneath the fuse link to reflect energy provided by the laser beam back into the fuse link, such that both the combination of the fins and the reflecting plate reduces the energy emitted by the laser beam required to blow the fuse structure.

摘要翻译： 在集成电路中，具有形成在沉积在半导体衬底上的绝缘层上的互连线，其提供与集成电路集成的元件之间的连接;由激光束可编程的熔丝结构，包括：熔化的细长熔丝链， 互连线 多个翅片与熔丝连接成一体并且共面，每个散热片横向延伸远离熔断体，以吸收由激光束发射的能量; 以及位于熔断体下方的反射板，以将由激光束提供的能量反射回熔丝链中，使得散热片和反射板的组合都减少了由熔丝结构所需的激光束发射的能量。

公开(公告)号：US6121074A

公开(公告)日：2000-09-19

申请号：US186515

申请日：1998-11-05

申请人： Frank Prein

发明人： Frank Prein

IPC分类号： H01L21/82 ,  H01L21/768 ,  H01L23/525 ,  H01L27/04

CPC分类号： H01L23/5258 ,  H01L2924/0002

摘要： A method of fabricating a fuse for a semiconductor memory, in accordance with the invention, includes the steps of forming a gate structure on a substrate including a polysilicon fuse layer and a gate cap layer disposed above the polysilicon fuse layer, forming an interlevel dielectric layer over the gate structure, depositing a dielectric layer over the interlevel dielectric layer, the dielectric layer and the interlevel dielectric layer both including a material which is selectively etchable relative to the gate cap layer and selectively etching contact holes through the dielectric layer and the interlevel dielectric layer such that at least one contact hole is formed over the gate structure and extends into the gate cap layer.

摘要翻译： 根据本发明的制造用于半导体存储器的熔丝的方法包括以下步骤：在包括多晶硅熔丝层和设置在多晶硅熔丝层上方的栅极盖层的衬底上形成栅极结构，形成层间电介质层 在栅极结构上方，在介电层之上沉积介电层，介电层和层间电介质层都包括相对于栅极盖层可选择性蚀刻的材料，并选择性地蚀刻通过介电层和层间电介质的接触孔 使得至少一个接触孔形成在栅极结构上方并延伸到栅极盖层中。

公开(公告)号：US6070004A

公开(公告)日：2000-05-30

申请号：US937764

申请日：1997-09-25

申请人： Frank Prein

发明人： Frank Prein

IPC分类号： H01L21/02 ,  H01L21/66 ,  G06F17/50 ,  G06F19/00 ,  G06K9/03

CPC分类号： H01L22/20

摘要： A method of fabricating semiconductor chips includes the steps of optimizing a number of chips that geometrically fit on a wafer and maximizing chip yield for the wafer by considering chips located in a normally rejectable location and utilizing yield probability data for the chip in the normally rejectable locations to weight the probability of an acceptable chip such that if the probability is above a threshold value the chips are not rejected. This results in an increased chip yield for semiconductor wafers.

摘要翻译： 一种制造半导体芯片的方法包括以下步骤：通过考虑位于正常可拒绝位置的芯片来优化几何装配在晶片上的芯片数量并最大化晶片的芯片产量，并且利用正常可排除位置的芯片的产量概率数据 为了加权可接受芯片的概率，使得如果概率高于阈值，则芯片不被拒绝。 这导致半导体晶片的芯片产量增加。

公开(公告)号：US5981302A

公开(公告)日：1999-11-09

申请号：US256048

申请日：1999-02-23

申请人： Frank Alswede ,  William Davies ,  Ronald Hoyer ,  Ron Mendelson ,  Frank Prein

发明人： Frank Alswede ,  William Davies ,  Ronald Hoyer ,  Ron Mendelson ,  Frank Prein

IPC分类号： H01L21/66 ,  H01L23/58 ,  H01L21/44

CPC分类号： H01L22/32 ,  Y10S257/923

摘要： A multi-layer test pad on a semiconductor wafer, which includes an underlying matrix of interconnected first pads, which are arranged in rows and columns. The multi-layer test pad includes an oxide layer disposed above the underlying matrix and in between the rows and columns. The multi-layer test pad further includes an overlying matrix of interconnected second pads disposed above the oxide layer. Each of the second pads completely overlaps at least nine of the first pads, including four oxide regions surrounding a center first pad of the nine of the first pads. The nine of the first pads are arranged as 3.times.3 block of the first pads.

摘要翻译： 半导体晶片上的多层测试焊盘，其包括以行和列排列的互连的第一焊盘的下层矩阵。 多层测试垫包括设置在下面的矩阵之上并且在行和列之间的氧化物层。 多层测试垫还包括布置在氧化物层上方的互连的第二焊盘的上覆矩阵。 每个第二焊盘完全重叠至少九个第一焊盘，包括围绕九个第一焊盘的中心第一焊盘的四个氧化物区域。 第一个焊盘中的九个排列为第一个焊盘的3x3块。

公开(公告)号：US5917197A

公开(公告)日：1999-06-29

申请号：US861465

申请日：1997-05-21

申请人： Frank Alswede ,  William Davies ,  Ronald Hoyer ,  Ron Mendelson ,  Frank Prein

发明人： Frank Alswede ,  William Davies ,  Ronald Hoyer ,  Ron Mendelson ,  Frank Prein

IPC分类号： H01L21/66 ,  H01L23/58

CPC分类号： H01L22/32 ,  Y10S257/923

摘要： A multi-layer test pad on a semiconductor wafer, which includes an underlying matrix of interconnected first pads, which are arranged in rows and columns. The multi-layer test pad includes an oxide layer disposed above the underlying matrix and in between the rows and columns. The multi-layer test pad further includes an overlying matrix of interconnected second pads disposed above the oxide layer. Each of the second pads completely overlaps at least nine of the first pads, including four oxide regions surrounding a center first pad of the nine of the first pads. The nine of the first pads are arranged as 3.times.3 block of the first pads.

摘要翻译： 半导体晶片上的多层测试焊盘，其包括以行和列排列的互连的第一焊盘的下层矩阵。 多层测试垫包括设置在下面的矩阵之上并且在行和列之间的氧化物层。 多层测试垫还包括布置在氧化物层上方的互连的第二焊盘的上覆矩阵。 每个第二焊盘完全重叠至少九个第一焊盘，包括围绕九个第一焊盘的中心第一焊盘的四个氧化物区域。 第一个焊盘中的九个排列为第一个焊盘的3x3块。

公开(公告)号：US06335228B1

公开(公告)日：2002-01-01

申请号：US09476726

申请日：1999-12-30

申请人： Robert T. Fuller ,  Frank Prein

发明人： Robert T. Fuller ,  Frank Prein

IPC分类号： H01L2182

CPC分类号： H01L23/5252 ,  H01L21/76877 ,  H01L2924/0002 ,  H01L2924/00

摘要： A manufacturing process for producing dynamic random access memories (DRAMs) having redundant components includes steps for concurrently forming normal (i.e. non-fused) contacts to components of the DRAMs and anti-fused contacts to the redundant components. The process by which the normal and anti-fused contacts are made is readily implemented using standard integrated circuit processing techniques. An anti-fuse contact (20) and a normal (i.e. non-fused) contact (10) are formed by opening respective contact areas in a dielectric (110), selectively forming an insulating layer (210) over the anti-fuse contact, applying polysilicon (212, 410) to cover the insulating layer of the anti-fuse contact and to fill the opening over the normal contact. In one embodiment of the invention, the circuit region served by the anti-fuse contact is subject to ion implantation (810) to improve its conductivity before the anti-fuse contact is formed. In another embodiment of the invention, the anti-fuse is formed in an isolated well (1212) on the integrated circuit device and a non-fused contact (1216) to the well is also provided to aid in blowing the anti-fuse.

摘要翻译： 用于产生具有冗余部件的动态随机存取存储器（DRAM）的制造方法包括用于同时向DRAM的组件和与多个组件的抗熔接触部形成正常（即非熔接）触点的步骤。 使用标准集成电路处理技术容易地实现正常和防熔接触点的制造过程。 通过在电介质（110）中打开相应的接触区域，在反熔丝接触件上选择性地形成绝缘层（210）来形成反熔丝接触件（20）和法线（即未熔接的）接触件（10） 施加多晶硅（212,410）以覆盖抗熔丝接触的绝缘层并填充正常触点上的开口。 在本发明的一个实施例中，由抗熔丝接触所服务的电路区域经受离子注入（810）以在形成抗熔丝接触之前提高其导电性。 在本发明的另一个实施例中，反熔丝形成在集成电路器件上的隔离阱（1212）中，并且还提供了与阱的非熔断接触（1216）以帮助吹入反熔丝。

公开(公告)号：US06174741B1

公开(公告)日：2001-01-16

申请号：US08994273

申请日：1997-12-19

申请人： Wilfried H{umlaut over (a)}nsch ,  Frank Prein ,  J{umlaut over (u)}rgen Faul

发明人： Wilfried H{umlaut over (a)}nsch ,  Frank Prein ,  J{umlaut over (u)}rgen Faul

IPC分类号： G01R3126

CPC分类号： H01L22/20 ,  H01L22/12 ,  H01L2924/0002 ,  H01L2924/00

摘要： Improved techniques for quantifying proximity effects during fabrication of integrated circuits are disclosed. The improved techniques use active features formed on a semiconductor wafer to quantify proximity effects. According to the improved techniques, a device performance quantity for an active feature is measured, and then a feature length for the active feature is determined in accordance with the measured device performance quantity. The fabrication processing can then be evaluated and/or compensated based on the determined feature length. In one example, the active feature can be a metal-oxide semiconductor (MOS) transistor and the device performance quantity can be current.

摘要翻译： 公开了用于量化集成电路制造过程中的邻近效应的改进技术。 改进的技术使用形成在半导体晶片上的活动特征来量化邻近效应。 根据改进的技术，测量有源特征的设备性能量，然后根据测量的设备性能量确定活动特征的特征长度。 然后可以基于所确定的特征长度来评估和/或补偿制造处理。 在一个示例中，有源特征可以是金属氧化物半导体（MOS）晶体管，并且器件性能量可以是电流。