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    Non-volatile memory cells without diffusion junctions
    1.
    发明申请
    Non-volatile memory cells without diffusion junctions 审中-公开
    不具有扩散结的非易失性存储单元

    公开(公告)号：US20060278913A1

    公开(公告)日：2006-12-14

    申请号：US11147976

    申请日：2005-06-08

    申请人： Andrei Mihnea ,  Behnam Moradi ,  Paul Rudeck ,  Aritome Seiichi ,  Di Li

    发明人： Andrei Mihnea ,  Behnam Moradi ,  Paul Rudeck ,  Aritome Seiichi ,  Di Li

    IPC分类号： H01L29/788 ,  H01L21/336 ,  G11C16/04

    CPC分类号： H01L27/115 ,  G11C16/0483 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

    摘要： A plurality of memory cell stacks are formed over a substrate. The substrate does not have diffusion regions between each memory cell stack to link the memory cells. The cells are formed close enough such that the memory cells are linked serially by the electric fields generated by each floating gate in the channel regions. In one embodiment, an n-layer is implanted at the top of the substrate to increase conductivity between cells. The select transistors can be linked to the serial string by diffusion regions or by interaction of the electric fields between the select transistor channel and the memory cell channel.

    摘要翻译： 多个存储单元堆叠形成在衬底上。 衬底在每个存储单元堆之间不具有扩散区，以连接存储单元。 电池形成得足够接近，使得存储器单元由通道区域中的每个浮动栅极产生的电场串联连接。 在一个实施例中，在衬底的顶部注入n层以增加电池之间的导电性。 选择晶体管可以通过扩散区域或通过选择晶体管沟道和存储单元通道之间的电场的相互作用而连接到串行串。

    Flash memory device and method of erasing
    3.
    发明授权
    Flash memory device and method of erasing 有权
    闪存设备和擦除方法

    公开(公告)号：US06798699B2

    公开(公告)日：2004-09-28

    申请号：US10373379

    申请日：2003-02-24

    申请人： Andrei Mihnea ,  Chun Chen ,  Paul Rudeck ,  Andrew R. Bicksler

    发明人： Andrei Mihnea ,  Chun Chen ,  Paul Rudeck ,  Andrew R. Bicksler

    IPC分类号： G11C1604

    CPC分类号： G11C16/3409 ,  G11C16/14 ,  G11C16/16 ,  G11C16/3404

    摘要： A non-volatile memory device for erasing a block of stack-gate single transistor flash memory cells performs an efficient and controllable mode of programming, referred to as block convergence. During an erase operation, one or more electrical erase pulses of fixed number, duration and voltage waveform are applied to memory cells in an addressable block of the memory device array to fully erase all bits in the block. A block convergence operation is applied simultaneously to all cells in the block, bringing a threshold voltage of cells, which may have become over-erased during the erase operation, to a controlled level. A reverse-bias pulse, capable of inducing band-to-band tunneling across one junction in the structure of the flash memory cells, is applied to a first junction. The other junction receives either a reverse bias or floating potential. The memory can implement several biasing schemes while performing the block convergence operation.

    摘要翻译： 用于擦除堆栈栅极单晶体管闪存单元的块的非易失性存储器件执行称为块会聚的有效且可控的编程模式。 在擦除操作期间，固定数量，持续时间和电压波形的一个或多个电擦除脉冲被施加到存储器件阵列的可寻址块中的存储器单元，以完全擦除块中的所有位。 块收敛操作同时应用于块中的所有单元，使得在擦除操作期间可能已经被擦除的单元的阈值电压达到受控的水平。 能够在闪速存储器单元的结构中的一个结点处引起带对带隧穿的反向偏置脉冲被施加到第一结。 另一端接收反向偏置或浮动电位。 存储器可以在执行块收敛操作时实现若干偏置方案。

    Flash memory device and method of erasing
    5.
    发明授权
    Flash memory device and method of erasing 有权

    公开(公告)号：US06563741B2

    公开(公告)日：2003-05-13

    申请号：US09772667

    申请日：2001-01-30

    申请人： Andrei Mihnea ,  Chun Chen ,  Paul Rudeck ,  Andrew R. Bicksler

    发明人： Andrei Mihnea ,  Chun Chen ,  Paul Rudeck ,  Andrew R. Bicksler

    IPC分类号： G11C1604

    CPC分类号： G11C16/3409 ,  G11C16/14 ,  G11C16/16 ,  G11C16/3404

    摘要： A non-volatile memory device includes an improved method for erasing a block of stack-gate single transistor flash memory cells. The memory performs an efficient and controllable mode of programming, referred to as block convergence. During an erase operation, one or more electrical erase pulses of fixed number, duration and voltage waveform are applied to memory cells in an addressable block of the memory device array. The erase pulse(s) fully erase all bits in the block. A block convergence operation is applied simultaneously to all cells in the block. The block convergence operation brings a threshold voltage of cells, which may have become over-erased during the erase operation, to a controlled level. A reverse-bias pulse, capable of inducing band-to-band tunnelling across one junction in the structure of the flash memory cells, is applied to a first junction. The other junction receives either a reverse bias or floating potential. The memory can implement several biasing schemes while performing the block convergence operation.

    Minimizing adjacent wordline disturb in a memory device
    6.
    发明申请
    Minimizing adjacent wordline disturb in a memory device 有权
    最小化存储设备中的相邻字线干扰

    公开(公告)号：US20060198222A1

    公开(公告)日：2006-09-07

    申请号：US11417575

    申请日：2006-05-04

    申请人： Paul Rudeck ,  Andrei Mihnea ,  Andrew Bicksler

    发明人： Paul Rudeck ,  Andrei Mihnea ,  Andrew Bicksler

    IPC分类号： G11C7/02

    CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3427

    摘要： A selected wordline that is coupled to cells for programming is biased with a programming voltage. The unselected wordlines that are adjacent to the selected wordline are biased at a first predetermined voltage. The remaining wordlines are biased at a second predetermined voltage that is greater than the first predetermined voltage. The first predetermined voltage is selected by determining what unselected, adjacent wordline bias voltage produces a minimized Vpass disturb in response to the selected wordline programming voltage.

    摘要翻译： 耦合到用于编程的单元的所选字线被编程电压偏置。 与所选字线相邻的未选字线被偏置在第一预定电压。 剩余的字线被偏置在大于第一预定电压的第二预定电压。 通过确定什么未选择的相邻字线偏置电压响应于所选择的字线编程电压产生最小化的Vcc通道干扰来选择第一预定电压。

    Punch-through diode steering element
    7.
    发明授权
    Punch-through diode steering element 有权
    穿通二极管转向元件

    公开(公告)号：US08575715B2

    公开(公告)日：2013-11-05

    申请号：US13571100

    申请日：2012-08-09

    申请人： Andrei Mihnea ,  Deepak C. Sekar ,  George Samachisa ,  Roy Scheuerlein ,  Li Xiao

    发明人： Andrei Mihnea ,  Deepak C. Sekar ,  George Samachisa ,  Roy Scheuerlein ,  Li Xiao

    IPC分类号： H01L29/66

    CPC分类号： G11C13/0007 ,  G11C13/003 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/72 ,  H01L27/24

    摘要： A storage system and method for forming a storage system that uses punch-through diodes as a steering element in series with a reversible resistivity-switching element is described. The punch-through diode allows bipolar operation of a cross-point memory array. The punch-through diode may have a symmetrical non-linear current/voltage relationship. The punch-through diode has a high current at high bias for selected cells and a low leakage current at low bias for unselected cells. Therefore, it is compatible with bipolar switching in cross-point memory arrays having resistive switching elements. The punch-through diode may be a N+/P−/N+ device or a P+/N−/P+ device.

    摘要翻译： 描述了一种用于形成使用穿通二极管作为与可逆电阻率切换元件串联的转向元件的存储系统的存储系统和方法。 穿通二极管允许交叉点存储器阵列的双极性操作。 穿通二极管可具有对称的非线性电流/电压关系。 穿通二极管在选择的电池的高偏压下具有高电流，对于未选择的电池，在低偏压下具有低泄漏电流。 因此，它与具有电阻式开关元件的交叉点存储器阵列中的双极开关兼容。 穿通二极管可以是N + / P- / N +器件或P + / N- / P +器件。

    Method for memory cell erasure with a programming monitor of reference cells
    8.
    发明授权
    Method for memory cell erasure with a programming monitor of reference cells 有权
    用参考单元的编程监视器进行存储单元擦除的方法

    公开(公告)号：US08514629B2

    公开(公告)日：2013-08-20

    申请号：US13602762

    申请日：2012-09-04

    申请人： Akira Goda ,  Andrei Mihnea

    发明人： Akira Goda ,  Andrei Mihnea

    IPC分类号： G11C16/16

    CPC分类号： G11C16/06 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/10 ,  G11C2211/5621 ,  G11C2211/5634

    摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for operating memory cells. One method includes: performing an erase operation on a selected group of memory cells, the selected group including a number of reference cells and a number of data cells; performing a programming monitor operation on the number of reference cells as part of the erase operation; and determining a number of particular operating parameters associated with operating the number of data cells at least partially based on the programming monitor operation performed on the number of reference cells.

    摘要翻译： 本公开的实施例提供用于操作存储器单元的方法，设备，模块和系统。 一种方法包括：对所选择的一组存储器单元执行擦除操作，所选择的组包括多个参考单元和多个数据单元; 对作为擦除操作的一部分的参考单元的数量进行编程监视操作; 以及至少部分地基于对参考单元的数量执行的编程监视操作来确定与操作所述数据单元的数量相关联的特定操作参数的数量。

    Junctionless TFT NAND flash memory
    9.
    发明授权
    Junctionless TFT NAND flash memory 有权
    无结点TFT NAND闪存

    公开(公告)号：US08395942B2

    公开(公告)日：2013-03-12

    申请号：US12848458

    申请日：2010-08-02

    申请人： George Samachisa ,  Johann Alsmeier ,  Andrei Mihnea

    发明人： George Samachisa ,  Johann Alsmeier ,  Andrei Mihnea

    IPC分类号： G11C11/34 ,  H01L29/06 ,  H01L29/76

    CPC分类号： H01L27/1214 ,  B82Y10/00 ,  G11C16/0483 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/1203 ,  H01L27/24 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

    摘要： A method of making a NAND string includes forming a semiconductor layer over a major surface of a substrate, patterning the semiconductor layer into an elongated nanowire shaped channel extending substantially parallel to the major surface of the substrate, forming a tunneling dielectric layer over the channel, forming a plurality of charge storage regions over the tunneling dielectric layer and undercutting the channel using the plurality of charge storage regions as mask. The channel has a narrower width than each charge storage region width, and an overhanging portion of each of the plurality of charge storage regions overhangs the channel. The method also includes forming a blocking dielectric layer over the plurality of charge storage regions, such that the blocking dielectric layer fills a space below the overhanging portion of each of the plurality of charge storage regions and forming a plurality of control gates over the blocking dielectric layer.

    摘要翻译： 制造NAND串的方法包括在衬底的主表面上形成半导体层，将半导体层图案化成基本上平行于衬底的主表面延伸的细长的纳米线形状的沟道，在沟道上形成隧穿介电层， 在隧道电介质层上形成多个电荷存储区域，并使用多个电荷存储区域作为掩模来对沟道进行底切。 通道具有比每个电荷存储区域宽度窄的宽度，并且多个电荷存储区域中的每一个的悬伸部分悬垂在通道上。 该方法还包括在多个电荷存储区域上形成阻挡电介质层，使得阻挡介电层填充多个电荷存储区域中的每一个的悬垂部分下面的空间，并在阻挡电介质上形成多个控制栅极 层。

    Method for memory cell erasure with a programming monitor of reference cells
    10.
    发明授权
    Method for memory cell erasure with a programming monitor of reference cells 有权
    用参考单元的编程监视器进行存储单元擦除的方法

    公开(公告)号：US07924623B2

    公开(公告)日：2011-04-12

    申请号：US12127415

    申请日：2008-05-27

    申请人： Akira Goda ,  Andrei Mihnea

    发明人： Akira Goda ,  Andrei Mihnea

    IPC分类号： G11C16/16

    CPC分类号： G11C16/06 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/10 ,  G11C2211/5621 ,  G11C2211/5634

    摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for operating memory cells. One method includes: performing an erase operation on a selected group of memory cells, the selected group including a number of reference cells and a number of data cells; performing a programming monitor operation on the number of reference cells as part of the erase operation; and determining a number of particular operating parameters associated with operating the number of data cells at least partially based on the programming monitor operation performed on the number of reference cells.

    摘要翻译： 本公开的实施例提供用于操作存储器单元的方法，设备，模块和系统。 一种方法包括：对所选择的一组存储器单元执行擦除操作，所选择的组包括多个参考单元和多个数据单元; 对作为擦除操作的一部分的参考单元的数量进行编程监视操作; 以及至少部分地基于对参考单元的数量执行的编程监视操作来确定与操作所述数据单元的数量相关联的特定操作参数的数量。