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    Calibration target for calibrating semiconductor wafer test systems
    1.
    发明授权
    Calibration target for calibrating semiconductor wafer test systems 有权
    用于校准半导体晶圆测试系统的校准目标

    公开(公告)号：US06420892B1

    公开(公告)日：2002-07-16

    申请号：US09685132

    申请日：2000-10-10

    申请人： Andrew J. Krivy ,  Warren M. Farnworth ,  David R. Hembree ,  Salman Akram ,  James M. Wark ,  John O. Jacobson

    发明人： Andrew J. Krivy ,  Warren M. Farnworth ,  David R. Hembree ,  Salman Akram ,  James M. Wark ,  John O. Jacobson

    IPC分类号： G01R3102

    CPC分类号： G01R35/005 ,  G01R1/073 ,  Y10T29/49197

    摘要： A calibration target for calibrating semiconductor wafer test systems including probe testers and probe card analyzers is provided. Also provided are calibration methods using the calibration target, and a method for fabricating the calibration target. The calibration target includes a substrate with various three dimensional alignment features formed thereon. A first type of alignment feature includes a contrast layer and an alignment fiducial formed on a tip portion thereof. The contrast layer and alignment fiducial are configured for viewing by a viewing device of the probe card analyzer, or the test system, to achieve X-direction and Y-direction calibration. A second type of alignment feature includes a conductive layer formed on a tip portion thereof, which is configured to electrically engage a contact on a check plate of the probe card analyzer, or a probe contact on a probe card of the test system, to achieve Z-direction calibration. The alignment features can be formed by forming raised members on a silicon substrate, and depositing and etching metal layers on the raised members.

    摘要翻译： 提供了用于校准包括探针测试仪和探针卡分析仪在内的半导体晶片测试系统的校准目标。 还提供了使用校准目标的校准方法以及用于制造校准目标的方法。 校准目标包括其上形成有各种三维对准特征的基板。 第一类型的对准特征包括形成在其顶端部分上的对比层和对准基准。 对比层和对准基准被配置为通过探针卡分析仪或测试系统的观察装置进行观察，以实现X方向和Y方向校准。 第二类型的对准特征包括形成在其尖端部分上的导电层，其被配置为与探针卡分析器的支撑板上的触点或测试系统的探针卡上的探针接触电接合，以实现 Z方向校准。 对准特征可以通过在硅衬底上形成凸起构件，以及在凸起构件上沉积和蚀刻金属层来形成。

    Calibration target for calibrating semiconductor wafer test systems
    2.
    发明授权
    Calibration target for calibrating semiconductor wafer test systems 失效
    用于校准半导体晶圆测试系统的校准目标

    公开(公告)号：US06239590B1

    公开(公告)日：2001-05-29

    申请号：US09084732

    申请日：1998-05-26

    申请人： Andrew J. Krivy ,  Warren M. Farnworth ,  David R. Hembree ,  Salman Akram ,  James M. Wark ,  John O. Jacobson

    发明人： Andrew J. Krivy ,  Warren M. Farnworth ,  David R. Hembree ,  Salman Akram ,  James M. Wark ,  John O. Jacobson

    IPC分类号： G01R104

    CPC分类号： G01R35/005 ,  G01R1/073 ,  Y10T29/49197

    摘要： A calibration target for calibrating semiconductor wafer test systems including probe testers and probe card analyzers is provided. Also provided are calibration methods using the calibration target, and a method for fabricating the calibration target. The calibration target includes a substrate with various three dimensional alignment features formed thereon. A first type of alignment feature includes a contrast layer and an alignment fiducial formed on a tip portion thereof. The contrast layer and alignment fiducial are configured for viewing by a viewing device of the probe card analyzer, or the test system, to achieve X-direction and Y-direction calibration. A second type of alignment feature includes a conductive layer formed on a tip portion thereof, which is configured to electrically engage a contact on a check plate of the probe card analyzer, or a probe contact on a probe card of the test system, to achieve Z-direction calibration. The alignment features can be formed by forming raised members on a silicon substrate, and depositing and etching metal layers on the raised members.

    摘要翻译： 提供了用于校准包括探针测试仪和探针卡分析仪在内的半导体晶片测试系统的校准目标。 还提供了使用校准目标的校准方法以及用于制造校准目标的方法。 校准目标包括其上形成有各种三维对准特征的基板。 第一类型的对准特征包括形成在其顶端部分上的对比层和对准基准。 对比层和对准基准被配置为通过探针卡分析仪或测试系统的观察装置进行观察，以实现X方向和Y方向校准。 第二类型的对准特征包括形成在其尖端部分上的导电层，其被配置为与探针卡分析器的支撑板上的触点或测试系统的探针卡上的探针接触电接合，以实现 Z方向校准。 对准特征可以通过在硅衬底上形成凸起构件，以及在凸起构件上沉积和蚀刻金属层来形成。

    Method for fabricating calibration target for calibrating semiconductor wafer test systems
    3.
    发明授权
    Method for fabricating calibration target for calibrating semiconductor wafer test systems 失效
    制造用于校准半导体晶片测试系统的校准目标的方法

    公开(公告)号：US06419844B1

    公开(公告)日：2002-07-16

    申请号：US09469339

    申请日：1999-12-20

    申请人： Andrew J. Krivy ,  Warren M. Farnworth ,  David R. Hembree ,  Salman Akram ,  James M. Wark ,  John O. Jacobson

    发明人： Andrew J. Krivy ,  Warren M. Farnworth ,  David R. Hembree ,  Salman Akram ,  James M. Wark ,  John O. Jacobson

    IPC分类号： H01L2100

    CPC分类号： G01R35/005 ,  G01R1/073 ,  Y10T29/49197

    摘要： A calibration target for calibrating semiconductor wafer test systems including probe testers and probe card analyzers is provided. Also provided are calibration methods using the calibration target, and a method for fabricating the calibration target. The calibration target includes a substrate with various three dimensional alignment features formed thereon. A first type of alignment feature includes a contrast layer and an alignment fiducial formed on a tip portion thereof. The contrast layer and alignment fiducial are configured for viewing by a viewing device of the probe card analyzer, or the test system, to achieve X-direction and Y-direction calibration. A second type of alignment feature includes a conductive layer formed on a tip portion thereof, which is configured to electrically engage a contact on a check plate of the probe card analyzer, or a probe contact on a probe card of the test system, to achieve Z-direction calibration. The alignment features can be formed by forming raised members on a silicon substrate, and depositing and etching metal layers on the raised members.

    摘要翻译： 提供了用于校准包括探针测试仪和探针卡分析仪在内的半导体晶片测试系统的校准目标。 还提供了使用校准目标的校准方法以及用于制造校准目标的方法。 校准目标包括其上形成有各种三维对准特征的基板。 第一类型的对准特征包括形成在其顶端部分上的对比层和对准基准。 对比层和对准基准被配置为通过探针卡分析仪或测试系统的观察装置进行观察，以实现X方向和Y方向校准。 第二类型的对准特征包括形成在其尖端部分上的导电层，其被配置为与探针卡分析器的支撑板上的触点或测试系统的探针卡上的探针接触电接合，以实现 Z向校准。 对准特征可以通过在硅衬底上形成凸起构件，以及在凸起构件上沉积和蚀刻金属层来形成。

    Test carrier with molded interconnect for testing semiconductor components
    5.
    发明授权
    Test carrier with molded interconnect for testing semiconductor components 失效
    带有模拟互连的测试载体，用于测试半导体元件

    公开(公告)号：US06544461B1

    公开(公告)日：2003-04-08

    申请号：US09677555

    申请日：2000-10-02

    申请人： David R. Hembree ,  Salman Akram ,  Warren M. Farnworth ,  Alan G. Wood ,  Derek Gochnour ,  John O. Jacobson ,  James M. Wark ,  Syed Sajid Ahmad

    发明人： David R. Hembree ,  Salman Akram ,  Warren M. Farnworth ,  Alan G. Wood ,  Derek Gochnour ,  John O. Jacobson ,  James M. Wark ,  Syed Sajid Ahmad

    IPC分类号： B29C4502

    CPC分类号： G01R1/0483

    摘要： A semiconductor carrier for testing semiconductor components, such as bare dice and chip scale packages, and a method for fabricating the carrier are provided. The carrier includes a molded plastic base, a lead frame, and an interconnect. The interconnect includes contacts for making temporary electrical connections with corresponding contacts (e.g., bond pads, solder balls) on the components. The carrier is fabricated by attaching the interconnect to the lead frame, and then molding the plastic base to the interconnect and lead frame. An alternate embodiment carrier includes a board to which multiple interconnects are molded or laminated. In addition, clip members retain the components on the board in electrical communication with the interconnects. A gasket may be used to protect the interconnect contacts during the molding step.

    摘要翻译： 提供了用于测试半导体部件的半导体载体，例如裸芯片和芯片级封装，以及制造载体的方法。 载体包括模制塑料基底，引线框架和互连件。 互连件包括用于与组件上的相应触点（例如，接合焊盘，焊球）进行临时电连接的触点。 通过将互连件附接到引线框架，然后将塑料基底模制到互连和引线框架来制造载体。 替代实施例的载体包括多个互连件模制或层压的板。 另外，夹子构件保持电路板上与组件电连通的组件。 可以在模制步骤期间使用垫圈来保护互连触点。

    Apparatus for testing semiconductor wafers
    7.
    发明授权
    Apparatus for testing semiconductor wafers 有权
    半导体晶片测试装置

    公开(公告)号：US6064216A

    公开(公告)日：2000-05-16

    申请号：US241553

    申请日：1999-02-01

    申请人： Warren M. Farnworth ,  Salman Akram ,  Alan G. Wood ,  David R. Hembree ,  James M. Wark ,  John O. Jacobson

    发明人： Warren M. Farnworth ,  Salman Akram ,  Alan G. Wood ,  David R. Hembree ,  James M. Wark ,  John O. Jacobson

    IPC分类号： G01R1/04 ,  G01R31/28 ,  G01R31/02

    CPC分类号： G01R1/0491 ,  G01R31/2886

    摘要： A method, apparatus and system for testing semiconductor wafers are provided. The method includes providing a wafer carrier to provide an electrical path for receiving and transmitting test signals to the wafer. The wafer carrier includes a base for retaining the wafer, and an interconnect having contact members configured to establish electrical communication with contact locations on the wafer. The wafer carrier can include one or more compressible spring members configured to bias the wafer and interconnect together in the assembled carrier. The wafer carrier can be assembled, with the wafer in alignment with the interconnect, using optical alignment techniques, and an assembly tool similar to aligner bonder tools used for flip chip bonding semiconductor dice. A system for use with the carrier can include a testing apparatus configured to apply test signals through the carrier to the wafer while the wafer is subjected to temperature cycling.

    摘要翻译： 提供了一种用于测试半导体晶片的方法，装置和系统。 该方法包括提供晶片载体以提供用于接收和传输测试信号到晶片的电路径。 晶片载体包括用于保持晶片的基座和具有被配置为与晶片上的接触位置建立电连通的接触构件的互连。 晶片载体可以包括被配置为偏置晶片并在组装的载体中互连在一起的一个或多个可压缩弹簧构件。 可以使用光学对准技术来组装晶片载体，其中晶片与互连对准，以及类似于用于倒装芯片接合半导体晶片的对准器焊接工具的组装工具。 与载体一起使用的系统可以包括测试装置，其被配置为在晶片受到温度循环的同时将测试信号通过载体施加到晶片。

    System and interconnect for making temporary electrical connections with bumped semiconductor components
    8.
    发明授权
    System and interconnect for making temporary electrical connections with bumped semiconductor components 有权
    用于与凸起的半导体部件进行临时电连接的系统和互连

    公开(公告)号：US5915977A

    公开(公告)日：1999-06-29

    申请号：US138612

    申请日：1998-08-24

    申请人： David R. Hembree ,  John O. Jacobson ,  James M. Wark ,  Warren M. Farnworth ,  Salman Akram ,  Alan G. Wood

    发明人： David R. Hembree ,  John O. Jacobson ,  James M. Wark ,  Warren M. Farnworth ,  Salman Akram ,  Alan G. Wood

    IPC分类号： G01R1/04 ,  H01L21/00 ,  H01R12/04 ,  H05K3/32 ,  H01R9/09

    CPC分类号： H01L21/67144 ,  G01R1/0408 ,  H05K3/326 ,  H01L2224/1601 ,  H01L2224/16237 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2224/81385

    摘要： An interconnect and system for establishing temporary electrical communication with semiconductor components having contact bumps are provided. The interconnect includes a substrate with patterns of contact members adapted to electrically contact the contact bumps. The substrate can be formed of a material such as ceramic, silicon, FR-4, or photo-chemically machineable glass. The contact members can be formed as recesses covered with conductive layers in electrical communication with conductors and terminal contacts on the substrate. Alternately, the contact members can be formed as projections adapted to penetrate the contact bumps, as microbumps with a rough textured surface, or as a deposited layer formed with recesses. The interconnect can be employed in a wafer level test system for testing dice contained on a wafer, or in a die level test system for testing bare bumped dice or bumped chip scale packages.

    摘要翻译： 提供了一种用于与具有接触凸块的半导体部件建立临时电连通的互连和系统。 互连包括具有适于电接触接触凸块的接触部件图案的基板。 衬底可由诸如陶瓷，硅，FR-4或光刻化学可加工玻璃的材料形成。 接触构件可以形成为覆盖有与衬底上的导体和端子触点电连通的导电层的凹陷。 或者，接触构件可以形成为适于穿透接触凸块的突起，作为具有粗糙纹理表面的微胶囊，或者形成为具有凹陷的沉积层。 互连可以用于晶片级测试系统中，用于测试包含在晶片上的骰子，或者用于测试裸露的骰子或凸起的芯片级封装的芯片级测试系统。

    Interconnect for testing semiconductor components having support members for preventing component flexure
    10.
    发明授权
    Interconnect for testing semiconductor components having support members for preventing component flexure 失效
    用于测试具有用于防止部件挠曲的支撑构件的半导体部件的互连

    公开(公告)号：US06407570B1

    公开(公告)日：2002-06-18

    申请号：US09479894

    申请日：2000-01-18

    申请人： Warren M. Farnworth ,  Mike Hess ,  David R. Hembree ,  James M. Wark ,  John O. Jacobson ,  Salman Akram

    发明人： Warren M. Farnworth ,  Mike Hess ,  David R. Hembree ,  James M. Wark ,  John O. Jacobson ,  Salman Akram

    IPC分类号： G01R3102

    CPC分类号： G01R1/0483 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49165

    摘要： A test carrier and an interconnect for testing semiconductor components, such as bare dice and chip scale packages, are provided. The carrier includes a base on which the interconnect is mounted, and a force applying mechanism for biasing the component against the interconnect. The interconnect includes interconnect contacts configured to make temporary electrical connections with component contacts (e.g., bond pads, solder balls). The interconnect also includes support members configured to physically contact the component, to prevent flexure of the component due to pressure exerted by the force applying mechanism. The support members can be formed integrally with the interconnect using an etching process. In addition, the support members can include an elastomeric layer to provide cushioning and to accommodate Z-direction dimensional variations.

    摘要翻译： 提供了测试载体和用于测试半导体部件（例如裸芯片和芯片级封装）的互连。 载体包括其上安装有互连件的基座，以及用于将部件抵靠互连件的力施加机构。 互连包括被配置为与部件触点（例如，焊盘，焊球）进行临时电连接的互连触头。 互连还包括被配置为物理地接触部件的支撑部件，以防止部件由于施力机构施加的压力而挠曲。 支撑构件可以使用蚀刻工艺与互连一体地形成。 此外，支撑构件可以包括弹性体层以提供缓冲并适应Z方向尺寸变化。