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公开(公告)号：US07383480B2
公开(公告)日：2008-06-03
申请号：US10896505
申请日：2004-07-22
IPC分类号： G01R31/28
CPC分类号： G11C29/32 , G01R31/318572 , G11C11/41 , G11C2029/3202
摘要： A method and system for scanning data from a specific latch in a matrix array of latches. The matrix array is made up of vertical selector lines and horizontal data lines. Each latch is coupled at an intersection of a selector line and a data line by a transistor. By turning on the transistor, the contents of the latch can be selectively read or written to.
摘要翻译： 一种用于从锁存器的矩阵阵列中的特定锁存器扫描数据的方法和系统。 矩阵阵列由垂直选择线和水平数据线组成。 每个锁存器通过晶体管耦合在选择器线和数据线的交叉点处。 通过接通晶体管，可以选择性地读取或写入锁存器的内容。
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公开(公告)号：US20080163019A1
公开(公告)日：2008-07-03
申请号：US12041144
申请日：2008-03-03
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G11C29/32 , G01R31/318572 , G11C11/41 , G11C2029/3202
摘要： A method and system for scanning data from a specific latch in a matrix array of latches. The matrix array is made up of vertical selector lines and horizontal data lines. Each latch is coupled at an intersection of a selector line and a data line by a transistor. By turning on the transistor, the contents of the latch can be selectively read or written to.
摘要翻译： 一种用于从锁存器的矩阵阵列中的特定锁存器扫描数据的方法和系统。 矩阵阵列由垂直选择线和水平数据线组成。 每个锁存器通过晶体管耦合在选择器线和数据线的交叉点处。 通过接通晶体管，可以选择性地读取或写入锁存器的内容。
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公开(公告)号：US20080144400A1
公开(公告)日：2008-06-19
申请号：US12041158
申请日：2008-03-03
IPC分类号： G11C7/10
CPC分类号： G11C29/32 , G01R31/318572 , G11C11/41 , G11C2029/3202
摘要： A method and system for scanning data from a specific latch in a matrix array of latches. The matrix array is made up of vertical selector lines and horizontal data lines. Each latch is coupled at an intersection of a selector line and a data line by a transistor. By turning on the transistor, the contents of the latch can be selectively read or written to.
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公开(公告)号：US07047468B2
公开(公告)日：2006-05-16
申请号：US10670832
申请日：2003-09-25
IPC分类号： G01R31/28
CPC分类号： G01R31/318572 , G11C29/003
摘要： A method and system for manipulating data in a state holding elements array. Process data is moved through the state holding elements array by a process controller. A separate scan controller scans data out of the state holding elements array by scanning data out of a group of cascaded latches where there are insufficient extra state holding elements in the group to enable normal scan. A multiplicity of local scan clocks are utilized to shift selected amounts of data only when a next state holding element in the group has been made available by clearing the contents of that next state holding element. In this way, any given latch, for the purpose of scan, is not a dedicated master or slave latch, but can act as either. This invention also addresses a circuit for the creation of the multiplicity of local clocks from a conventional LSSD clock source.
摘要翻译： 用于在保持元素数组的状态下操作数据的方法和系统。 过程控制器将过程数据移动通过状态保持元素数组。 单独的扫描控制器通过从组中不充足的额外状态保持元件的一组级联锁存器扫描数据来扫描状态保持元件阵列中的数据，以启用正常扫描。 仅当通过清除该下一状态保持元件的内容已经使该组中的下一状态保持元件可用时，才使用多个本地扫描时钟来移位所选择的数据量。 以这种方式，为了扫描的目的，任何给定的锁存器不是专用的主器件或从器件锁存器，而是可以作为任一个。 本发明还涉及用于从常规LSSD时钟源产生多个本地时钟的电路。
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5.发明授权Implementing instruction set architectures with non-contiguous register file specifiers 有权用不连续的寄存器文件说明符来实现指令集体系结构公开(公告)号：US07793081B2
公开(公告)日：2010-09-07
申请号：US12062131
申请日：2008-04-03
IPC分类号： G06F9/30
CPC分类号： G06F9/3012 , G06F9/30101 , G06F9/30112 , G06F9/30138 , G06F9/30145 , G06F9/3016 , G06F9/30167 , G06F9/30174 , G06F9/30181 , G06F9/30185 , G06F9/3802 , G06F9/382 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3885
摘要： There are provided methods and computer program products for implementing instruction set architectures with non-contiguous register file specifiers. A method for processing instruction code includes processing a fixed-width instruction of a fixed-width instruction set using a non-contiguous register specifier of a non-contiguous register specification. The fixed-width instruction includes the non-contiguous register specifier.
摘要翻译： 提供了用于实现具有非连续寄存器文件说明符的指令集架构的方法和计算机程序产品。 一种用于处理指令代码的方法包括使用非连续寄存器规范的非连续寄存器说明符来处理固定宽度指令集的固定宽度指令。 固定宽度指令包括不连续的寄存器说明符。
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公开(公告)号：US20090019341A1
公开(公告)日：2009-01-15
申请号：US11776810
申请日：2007-07-12
CPC分类号： G06F12/0893 , G06F11/1064 , G06F2212/1056 , G11C7/1006 , G11C11/406 , G11C11/4096 , G11C2029/0411 , G11C2207/2245 , G11C2211/4062 , Y02D10/13
摘要： Apparatus for passively tracking expired data in a dynamic memory includes a time stamp memory configurable for storing information relating to a refresh status of one or more corresponding data entries in the dynamic memory. The apparatus further includes a timer configurable for defining a desired window of time in which a refresh operation of data in the dynamic memory is to occur in order to ensure that the data is valid. Control circuitry is coupled to the time stamp memory and to the timer. The control circuitry is operative to manage the information stored in the time stamp memory relating to the refresh status of the one or more corresponding data entries in the dynamic memory.
摘要翻译： 用于在动态存储器中被动跟踪过期数据的装置包括可配置用于存储与动态存储器中的一个或多个相应数据条目的刷新状态相关的信息的时间戳存储器。 该装置还包括定时器，其可配置用于定义要在其中发生动态存储器中的数据的刷新操作的期望时间窗口，以便确保数据有效。 控制电路耦合到时间戳存储器和定时器。 控制电路用于管理存储在时间戳存储器中的与动态存储器中的一个或多个相应数据条目的刷新状态有关的信息。
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7.发明授权公开(公告)号：US07349288B1
公开(公告)日：2008-03-25
申请号：US11538877
申请日：2006-10-05
IPC分类号： G11C8/00
CPC分类号： G11C8/10
摘要： An ultra high speed address decoder uses a combination of Domino logic circuits and LSDL logic circuits. N address bits are converted into N logic true address bits and N complementary address bits. A partial address decoder generates two bit groups using selected of the N logic true address bits and N complementary address bits in NOR logic structures such only two cascaded NFETS are used in a logic tree. The bit groups are partitioned to optimize the layout of the parallel bit lines in the address decoder.
摘要翻译： 超高速地址解码器使用Domino逻辑电路和LSDL逻辑电路的组合。 N个地址位转换为N个逻辑真地址位和N个互补地址位。 部分地址解码器使用NOR逻辑结构中的N个逻辑真地址位和N个互补地址位来生成两个位组，因此在逻辑树中仅使用两个级联的NFETS。 这些位组被划分以优化地址解码器中的并行位线的布局。
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8.发明授权公开(公告)号：US06667555B2
公开(公告)日：2003-12-23
申请号：US10301196
申请日：2002-11-21
IPC分类号： H01L2348
CPC分类号： H05K1/144 , H01L25/105 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A spacer-connector stud comprises a stacked array of glass epoxy laminates, each laminate having a copper layer laminated thereto. The top and bottom laminates of the stud include a spatial array of thermal contacts suitable as a footprint for C4 bump technology. A location is selected on a circuitized base card to accommodate the laminated stud. The stud has a thickness greater than twice the thickness of the components attached to the card. The thermal contacts on the stud, typically solderable, join to a wiring array on the card. A second multi-chip module card having attached and interconnected components on both sides of the second card is mechanically aligned with the based card and pressed against the contacts on the top layer of the stud to form an assembly. The assembly is heated causing the second card to become soldered to the contact footprint on the stud.
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公开(公告)号：US08605489B2
公开(公告)日：2013-12-10
申请号：US13307884
申请日：2011-11-30
CPC分类号： G11C11/4085 , G11C11/406 , G11C11/4072 , G11C11/4074 , G11C11/4094
摘要： A memory device includes memory cells, each of the memory cells having corresponding bit and word lines connected thereto for accessing the memory cells, a word line circuit coupled with at least one word line, and a bit line circuit coupled with at least one bit line. The memory device further includes at least one control circuit coupled with the bit and word line circuits. The control circuit is operative to cause state information to be stored in the memory cells. At least one switching element selectively connects the memory cells, the bit and word line circuits, and the control circuit to at least one power supply as a function of at least one control signal. The control circuit generates the control signal for disconnecting at least portions of the word line and bit line circuits from the power supply while state information is retained in the memory cells.
摘要翻译： 存储器件包括存储器单元，每个存储器单元具有连接到其上的相应位和字线用于访问存储器单元，与至少一个字线耦合的字线电路和与至少一个位线耦合的位线电路 。 存储器件还包括与位和字线电路耦合的至少一个控制电路。 控制电路用于使状态信息存储在存储单元中。 至少一个开关元件将存储器单元，位和字线电路以及控制电路选择性地连接到作为至少一个控制信号的函数的至少一个电源。 控制电路产生控制信号，用于将字线和位线电路的至少一部分与电源断开，同时将状态信息保留在存储单元中。
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公开(公告)号：US08020073B2
公开(公告)日：2011-09-13
申请号：US11776810
申请日：2007-07-12
IPC分类号： G11C29/00
CPC分类号： G06F12/0893 , G06F11/1064 , G06F2212/1056 , G11C7/1006 , G11C11/406 , G11C11/4096 , G11C2029/0411 , G11C2207/2245 , G11C2211/4062 , Y02D10/13
摘要： Apparatus for passively tracking expired data in a dynamic memory includes a time stamp memory configurable for storing information relating to a refresh status of one or more corresponding data entries in the dynamic memory. The apparatus further includes a timer configurable for defining a desired window of time in which a refresh operation of data in the dynamic memory is to occur in order to ensure that the data is valid. Control circuitry is coupled to the time stamp memory and to the timer. The control circuitry is operative to manage the information stored in the time stamp memory relating to the refresh status of the one or more corresponding data entries in the dynamic memory.
摘要翻译： 用于在动态存储器中被动跟踪过期数据的装置包括可配置用于存储与动态存储器中的一个或多个相应数据条目的刷新状态相关的信息的时间戳存储器。 该装置还包括定时器，其可配置用于定义要在其中发生动态存储器中的数据的刷新操作的期望时间窗口，以便确保数据有效。 控制电路耦合到时间戳存储器和定时器。 控制电路用于管理存储在时间戳存储器中的与动态存储器中的一个或多个相应数据条目的刷新状态有关的信息。
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