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1.发明授权
公开(公告)号：US5852748A
公开(公告)日：1998-12-22
申请号：US578209
申请日：1995-12-29
CPC分类号： G06F5/10
摘要： The present invention provides a circuit for generating a programmable write-read word line equality signal in FIFO buffers. The present invention significantly reduces the gate delay associated in producing the write-read word line equality signal. The delay is reduced from a typical 30-50 gate delays, to as little as four gate delays. The present invention accomplishes this by processing several bit operations in parallel and making the general circuit architecture symmetric. The delay is constant in all of the parallel paths but amounts to only a short delay for the final WREQ output.
摘要翻译： 本发明提供了一种用于在FIFO缓冲器中产生可编程写入读取字线相等信号的电路。 本发明显着地减少了与产生写入读取字线相等信号相关联的门延迟。 延迟从典型的30-50门延迟减少到只有四个门延迟。 本发明通过并行处理几位操作并使通用电路架构对称来实现。 所有并行路径的延迟是恒定的，但对于最终的WREQ输出而言，延迟仅为短暂的延迟。
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公开(公告)号：US5642318A
公开(公告)日：1997-06-24
申请号：US567544
申请日：1995-12-05
CPC分类号： G11C29/46 , G11C29/003
摘要： The present invention provides a system for testing a memory array and corresponding support circuitry. The present invention provides a highly efficient testing mode to be entered that allows any type of advanced testing to be performed on the memory array without regard to the restrictions imposed by the various status flags that may be present. The testing mode can be entered by a completely user-defined mechanism. During this testing mode, the user has complete control over the contents of the memory array and can also have complete control over the positioning of the write word line with respect to the read word line without, for example, any write-read word line pointer equality signals being generated. In one example of the present invention used in a FIFO, testing times required for data retention testing are reduced from approximately six seconds to approximately 500.mu. seconds for each part tested, since the entire internal memory core of the FIFO can be tested in a single pass without regard to the external depth of the FIFO.
摘要翻译： 本发明提供了一种用于测试存储器阵列和相应的支持电路的系统。 本发明提供一种要输入的高效测试模式，其允许对存储器阵列执行任何类型的高级测试，而不考虑可能存在的各种状态标志所施加的限制。 可以通过完全由用户定义的机制输入测试模式。 在该测试模式期间，用户可以完全控制存储器阵列的内容，并且还可以完全控制写字线相对于读字线的位置，而不需要例如任何写读字线指针 生成相等信号。 在FIFO中使用的本发明的一个示例中，对于每个测试部分，数据保持测试所需的测试时间从大约六秒减少到大约500μs，因为FIFO的整个内部存储器核心可以在单个 通过而不考虑FIFO的外部深度。
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3.发明授权Clocking scheme for independently reading and writing multiple width words from a memory array 失效用于独立地从存储器阵列读取和写入多个宽度字的时钟方案公开(公告)号：US06510486B1
公开(公告)日：2003-01-21
申请号：US08621487
申请日：1996-03-25
IPC分类号： G06F1200
CPC分类号： G06F5/10 , G06F5/00 , G11C7/1018 , G11C7/103 , G11C7/1075
摘要： The present invention provides a circuit for writing a particular sized data word from a common input to a number of individual memory cells in a memory array and reading a particular sized data word from the individual memory cells to a common output. The size of the word written to the memory cells can be larger, smaller or the same as the size of the word read from the memory array. The present invention uses a multi-bit write counter to distribute a write timing signal to a number of multiplexer blocks and a multi-bit read counter to distribute a read timing signal to a number of sense amplifier blocks. Each of the multiplexer blocks receives both a data input signal from the common input and the write timing signal continuously when the circuit is in operation. Each of the sense amplifier blocks receives data from the memory array and a read timing signal at all times. When a particular read timing signal is present at a sense amplifier, the output signal containing a fixed width data word is received from one or more of the corresponding memory arrays and is presented to the common output. The present invention reduces the number of internal signal lines necessary to implement the control function and allows for easy modification to both read and write multiple width words to and from the memory array.
摘要翻译： 本发明提供了一种用于将特定大小的数据字从公共输入写入存储器阵列中的多个单独存储器单元并且将特定大小的数据字从各个存储器单元读取到公共输出的电路。 写入存储器单元的字的大小可以比从存储器阵列读取的字的大小更小或相同。 本发明使用多比特写计数器将写定时信号分配给多个多路复用器块和多比特读计数器，以将读定时信号分配到多个读出放大器块。 当电路运行时，多路复用器块中的每一个都接收来自公共输入端的数据输入信号和写定时信号。 每个读出放大器块一直从存储器阵列接收数据和读取定时信号。 当特定的读定时信号存在于读出放大器时，从一个或多个对应的存储器阵列接收包含固定宽度数据字的输出信号，并将其呈现给公共输出。 本发明减少了实现控制功能所需的内部信号线的数量，并且允许容易地对存储器阵列的读取和写入多个宽度字进行修改。
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4.发明授权Redundancy circuit and method for providing word lines driven by a shift register 失效用于提供由移位寄存器驱动的字线的冗余电路和方法
公开(公告)号：US5812465A
公开(公告)日：1998-09-22
申请号：US691357
申请日：1996-08-02
CPC分类号： G11C29/785 , G11C29/832
摘要： The present invention disables defective rows in a FIFO or other buffer where the word lines of the FIFO buffer are driven by a shift register scheme. Additional enabled rows may be placed within the normal memory array. The additional enabled rows are substituted, as needed, for one or more defective rows. As a result, a defective row can be disabled without effecting the operation of the FIFO, particularly the read or write data path. In one example, the disabling effect is achieved by using one or more laser fuses. The present invention can be used to effectively bypass any single shift register element or a multiple number of shift register elements.
摘要翻译： 本发明禁止FIFO或其他缓冲器中的有缺陷的行，其中FIFO缓冲器的字线由移位寄存器方案驱动。 额外启用的行可以放置在正常的存储器阵列内。 根据需要，对一个或多个有缺陷的行替换附加的已启用的行。 结果，可以禁用有缺陷的行，而不影响FIFO的操作，特别是读或写数据路径。 在一个示例中，通过使用一个或多个激光熔丝来实现禁用效果。 本发明可用于有效地绕过任何单个移位寄存器元件或多个移位寄存器元件。
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5.发明授权Multiple word width memory array clocking scheme for reading words from a memory array 失效用于从存储器阵列读取字的多字宽存储器阵列时钟方案
公开(公告)号：US5682356A
公开(公告)日：1997-10-28
申请号：US584530
申请日：1996-01-11
申请人： Roland T. Knaack
发明人： Roland T. Knaack
CPC分类号： G11C7/1006
摘要： The present invention provides a circuit for distributing data from a number of individual memory cells in a memory array to a common output. The present invention uses a multi-bit counter to distribute a timing signal to a number of sense amplifier blocks. Each of the sense amplifier blocks receives both a data input signal from the memory array and the timing signal at all times. When a particular timing signal is present at a sense amplifier, the output signal containing a fixed width data word is received from the corresponding memory array and is presented to the output. The present invention reduces the number of internal signal lines necessary to implement the control function and allows for easy modification to read multiple width words from the memory array.
摘要翻译： 本发明提供一种用于将数据从存储器阵列中的多个单独存储单元分配到公共输出的电路。 本发明使用多位计数器将定时信号分配到多个读出放大器块。 每个读出放大器块一直接收来自存储器阵列的数据输入信号和定时信号。 当在读出放大器上存在特定定时信号时，从相应的存储器阵列接收包含固定宽度数据字的输出信号，并将其提供给输出。 本发明减少了实现控制功能所需的内部信号线的数量，并且允许容易地从存储器阵列读取多个宽度字的修改。
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6.发明授权Programmable clock drivers that support CRC error checking of configuration data during program restore operations 有权可编程时钟驱动程序，支持在程序还原操作期间对配置数据进行CRC错误检查公开(公告)号：US07196562B1
公开(公告)日：2007-03-27
申请号：US10979979
申请日：2004-11-03
IPC分类号： H03L7/06
CPC分类号： H03L7/0996 , G06F1/08 , G06F11/1004 , H03K5/00006 , H03K5/13 , H03K5/1565 , H03K2005/00052 , H03K2005/00058
摘要： A packaged integrated circuit device includes a nonvolatile memory device and a programmable clock driver circuit therein. The memory device may be provided as an EEPROM device that is disposed on a first integrated circuit substrate and the programmable clock driver circuit may be disposed on a second integrated circuit substrate. The programmable clock driver circuit includes a control circuit and a clock generator therein. The control circuit is configured to detect an error(s) in configuration data that is used by the programmable clock driver circuit. This configuration data is read from the nonvolatile memory and stored in volatile program registers during program restore operations. The control circuit is further configured to automatically idle the clock generator in response to detecting the error in the configuration data. This automatic idling of the clock generator may include operations to set the clock generator at a default setting (e.g., minimum frequency), which applies to all output banks of the driver circuit.
摘要翻译： 封装的集成电路器件包括非易失性存储器件和其中的可编程时钟驱动器电路。 存储器件可以被提供为设置在第一集成电路衬底上的EEPROM器件，并且可编程时钟驱动器电路可以被布置在第二集成电路衬底上。 可编程时钟驱动电路包括控制电路和时钟发生器。 控制电路被配置为检测由可编程时钟驱动器电路使用的配置数据中的错误。 在程序恢复操作期间，从非易失性存储器读取该配置数据并存储在易失性程序寄存器中。 控制电路还被配置为响应于检测到配置数据中的错误而自动地使时钟发生器空闲。 时钟发生器的这种自动空闲可以包括将时钟发生器设置为适用于驱动器电路的所有输出组的默认设置（例如，最小频率）的操作。
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7.发明授权Integrated DDR/SDR flow control managers that support multiple queues and MUX, DEMUX and broadcast operating modes 有权集成DDR / SDR流量控制管理器，支持多个队列和MUX，DEMUX和广播操作模式公开(公告)号：US07082071B2
公开(公告)日：2006-07-25
申请号：US10881022
申请日：2004-06-30
申请人： Roland T. Knaack , David Stuart Gibson , Mario Montana , Mario Au , Stewart Speed , Srinivas Satish Babu Bamdhamravuri , Uksong Kang
发明人： Roland T. Knaack , David Stuart Gibson , Mario Montana , Mario Au , Stewart Speed , Srinivas Satish Babu Bamdhamravuri , Uksong Kang
IPC分类号： G11C7/00
CPC分类号： G06F5/06
摘要： An integrated circuit chip includes a plurality of independent FIFO memory devices that are each configured to support all four combinations of DDR and SDR write modes and DDR and SDR read modes and collectively configured to support all four multiplexer, demultiplexer, broadcast and multi-Q operating modes.
摘要翻译： 集成电路芯片包括多个独立的FIFO存储器件，其各自被配置为支持DDR和SDR写入模式以及DDR和SDR读取模式的所有四种组合，并且共同配置为支持所有四个多路复用器，解复用器，广播和多Q操作 模式。
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公开(公告)号：US5968190A
公开(公告)日：1999-10-19
申请号：US741953
申请日：1996-10-31
申请人： Roland T. Knaack
发明人： Roland T. Knaack
CPC分类号： G11C29/789 , G11C29/4401
摘要： The present invention concerns a circuit and method to automatically test and disable defective rows in a FIFO or other buffer where the wordlines or rows of the FIFO buffer are driven by a shift register scheme. Additional enabled rows may be placed within the normal memory array. The additional enabled rows are substituted, as needed, for one or more defective rows. As a result, a defective row can be automatically disabled without effecting the operation of the FIFO, particularly the read or write data path. In one example, the disabling effect is achieved by using a comparison circuit to determine if the words read from the memory are accurate. The present invention can be used to effectively bypass any single shift register element or a multiple number of shift register elements.
摘要翻译： 本发明涉及一种在FIFO或其他缓冲器中自动测试和禁用有缺陷的行的电路和方法，其中FIFO缓冲器的字线或行由移位寄存器方案驱动。 额外启用的行可以放置在正常的存储器阵列内。 根据需要，对一个或多个有缺陷的行替换附加的已启用的行。 结果，可以自动禁用有缺陷的行，而不影响FIFO的操作，特别是读或写数据路径。 在一个示例中，通过使用比较电路来确定从存储器读取的单词是否准确，可以实现禁用效果。 本发明可用于有效地绕过任何单个移位寄存器元件或多个移位寄存器元件。
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9.发明授权DRAM interface circuits having enhanced skew, slew rate and impedance control 有权具有增强的偏移，转换速率和阻抗控制的DRAM接口电路公开(公告)号：US07079446B2
公开(公告)日：2006-07-18
申请号：US10916901
申请日：2004-08-12
申请人： Paul Murtagh , Roland T. Knaack
发明人： Paul Murtagh , Roland T. Knaack
IPC分类号： G11C8/00
CPC分类号： G11C7/22
摘要： Fully-buffered dual in-line memory modules (FB-DIMM) include advanced memory buffers (AMBs) having enhanced skew, slew rate and output impedance control. The AMB includes user accessible registers that can be programmed to carefully control the edge placement (or phase) of signals generated from the AMB to multiple DRAMs on the module. This control of edge placement, which may be performed independently for each group of signals: clock (CLK, CLK#), command (RAS, CAS, WE), address (including bank address), data (DQ) and data strobe (DQS), provides 360 degrees of control (or one period). This means that any group of signals can be moved independently by one complete period relatively to any other group.
摘要翻译： 全缓冲双列直插式存储器模块（FB-DIMM）包括具有增强的偏移，转换速率和输出阻抗控制的高级存储器缓冲器（AMB）。 AMB包括可以编程的用户可访问寄存器，以便仔细地控制从AMB生成的信号到模块上的多个DRAM的边缘放置（或相位）。 时钟（CLK，CLK＃），命令（RAS，CAS，WE），地址（包括存储体地址），数据（DQ）和数据选通（DQS）的每组信号可以独立执行边缘放置的这种控制 ），提供360度的控制（或一个周期）。 这意味着任何一组信号可以相对于任何其他组独立地移动一整个周期。
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10.发明授权Integrated circuit memory devices having partitioned multi-port memory arrays therein for increasing data bandwidth and methods of operating same 失效具有分割多端口存储器阵列的集成电路存储器件用于增加数据带宽以及其操作方法
公开(公告)号：US5978307A
公开(公告)日：1999-11-02
申请号：US82856
申请日：1998-05-21
CPC分类号： G11C8/16 , G11C7/1006 , G11C7/1051 , G11C7/1075 , G11C8/12
摘要： Multi-port memory arrays having partitioned registers therein are provided. The registers are partitioned into subarrays so that at least two columns of a selected register can be simultaneously written to (or read from) using first and second input/output driver circuits. These first and second input/output driver circuits are electrically coupled to respective read and write data ports at opposing ends of the memory array. Control logic and first and second input/output driver circuits are provided for writing a first portion of a word of data into a first subarray while simultaneously writing a second portion of the word of data into a second subarray. Here, the first and second portions may comprise the least significant and most significant bytes of the word of data. The first input/output driver circuit is also electrically coupled to first read and write data lines at a first end of the memory array and the second input/output driver circuit is electrically coupled to second read and write data lines at a second end of the memory array. A data flow control circuit containing a crosspoint switch is also provided for routing input and output data between input and output registers and the first and second input/output driver circuits. The data flow control circuit, preferred arrangement of memory cells and dual input/output driver circuits also enables 2.times., 1.times. and 1/2.times. word width capability which can be selected by a user, for example.
摘要翻译： 提供其中具有分区寄存器的多端口存储器阵列。 这些寄存器被划分为子阵列，使得可以使用第一和第二输入/输出驱动器电路同时将所选寄存器的至少两列同时写入（或从中读取）。 这些第一和第二输入/输出驱动器电路电耦合到存储器阵列的相对端处的相应的读取和写入数据端口。 提供控制逻辑和第一和第二输入/输出驱动器电路，用于将数据字的第一部分写入第一子阵列，同时将数据字的第二部分写入第二子阵列。 这里，第一和第二部分可以包括数据字的最低有效字节和最高有效字节。 第一输入/输出驱动器电路还在存储器阵列的第一端处电耦合到第一读取和写入数据线，并且第二输入/输出驱动器电路在第二输入/输出驱动器电路的第二端处电耦合到第二读取和写入数据线 内存阵列 还提供了包含交叉点开关的数据流控制电路，用于在输入和输出寄存器以及第一和第二输入/输出驱动器电路之间路由输入和输出数据。 数据流控制电路，存储单元和双输入/输出驱动器电路的优选布置还使得可以由用户选择的2x，1x和+ E，fra1 / 2 + EE×字宽度能力。
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