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1.发明授权Compensation for low gain bipolar transistors in voltage and current reference circuits 失效电压和电流参考电路中低增益双极晶体管的补偿
公开(公告)号：US5349286A
公开(公告)日：1994-09-20
申请号：US79665
申请日：1993-06-18
CPC分类号： G05F3/30
摘要： A bandgap reference circuit 30 includes a current generation circuit 32, a voltage generation circuit 34 connected to current generation circuit 32, and a compensation circuit connected to current generation circuit 32 and voltage generation circuit 34. Current generation circuit 32 sources a current to voltage generation circuit 34 which translates the current into a voltage. Compensation circuit 36 monitors current generation circuit 32 and provides a supplemental current to voltage generation circuit 34. Voltage generation circuit 34 receives the supplemental current and translates it into a supplemental voltage. The summation of the voltage produced by the current received by current generation circuit 32 and the supplemental voltage produced by the supplemental current received by compensation circuit 36 produces a stable reference voltage.
摘要翻译： 带隙参考电路30包括电流产生电路32，连接到电流产生电路32的电压产生电路34以及连接到电流产生电路32和电压产生电路34的补偿电路。电流产生电路32产生电流到电压产生 电路34，其将电流转换成电压。 补偿电路36监视电流产生电路32并向电压产生电路34提供补充电流。电压产生电路34接收补充电流并将其转换成补充电压。 由电流发生电路32接收的电流产生的电压和由补偿电路36接收的补充电流产生的补充电压的总和产生稳定的参考电压。
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2.发明授权Reducing the natural current limit in a power MOS device by reducing the gate-source voltage 失效通过降低栅源电压降低功率MOS器件的自然电流限制
公开(公告)号：US5579193A
公开(公告)日：1996-11-26
申请号：US486926
申请日：1995-06-07
IPC分类号： H03K17/082 , H02H7/10
CPC分类号： H03K17/0822
摘要： In accordance with the present invention, an output current limit circuit for protecting a power MOS output device of an integrated circuit from an excessive drain current comprises a power MOS device 110, sensing circuitry 30 to sense a predetermined trigger current, and limitation circuitry 20 to reduce a gate-source voltage on MOS output device 110 to a predetermined approximately fixed value. A drain current I.sub.D flows through power MOS device 110 from output terminal 102 in response to the gate-source voltage. A short circuit condition may allow an excessive amount of drain current I.sub.D to flow through output terminal 102. The gate-source voltage is reduced in response to sensing the trigger current. Reducing the gate-source voltage raises a drain-source resistance of MOS device 110 and reduces drain current I.sub.D so that MOS device 110 is not damaged by the short circuit condition.
摘要翻译： 根据本发明，用于保护集成电路的功率MOS输出装置与过剩漏极电流的输出限流电路包括功率MOS器件110，检测电路30以感测预定的触发电流，以及限制电路20至 将MOS输出装置110上的栅极 - 源极电压降低到预定的大致固定值。 漏极电流ID响应于栅极 - 源极电压从输出端子102流过功率MOS器件110。 短路状态可允许过量的漏极电流ID流过输出端子102.响应于感测触发电流，栅极 - 源极电压被降低。 降低栅极 - 源极电压会提高MOS器件110的漏极 - 源极电阻并且减少漏极电流ID，使得MOS器件110不会被短路状态损坏。
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公开(公告)号：US5812006A
公开(公告)日：1998-09-22
申请号：US739375
申请日：1996-10-29
申请人： Ross E. Teggatz , Joseph A. Devore , Kenneth G. Buss , Thomas A. Schmidt , Taylor R. Efland , Stephen C. Kwan
发明人： Ross E. Teggatz , Joseph A. Devore , Kenneth G. Buss , Thomas A. Schmidt , Taylor R. Efland , Stephen C. Kwan
IPC分类号： H03K17/06 , H03K17/082 , H03K5/08
CPC分类号： H03K17/063 , H03K17/0822
摘要： An optimized power output clamping structure, includes a power output transistor having a first breakdown voltage and a breakdown structure having a second breakdown voltage coupled to the power output transistor. The second breakdown voltage is less than the first breakdown voltage and follows the first breakdown voltage across all temperature and semiconductor process variations. This feature allows a reduction in breakdown voltage guardbanding and increases output structure reliability. A method of protecting a circuit from inductive flyback is also disclosed. The method includes the steps of driving an inductive load with drive circuitry, turning off the inductive load, and clamping an inductive voltage at a voltage magnitude that protects the drive circuitry from breakdown across all temperature and processing variations.
摘要翻译： 优化的功率输出钳位结构包括具有第一击穿电压的功率输出晶体管和具有耦合到功率输出晶体管的第二击穿电压的击穿结构。 第二击穿电压小于第一击穿电压，并且遵循所有温度和半导体工艺变化的第一击穿电压。 该特征允许降低击穿电压保护带并增加输出结构的可靠性。 还公开了一种保护电路免受感应回扫的方法。 该方法包括以下步骤：利用驱动电路驱动感性负载，关闭感性负载，以及钳位感应电压，电压幅度保护驱动电路不受所有温度和处理变化的影响。
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4.发明授权Reducing the natural current limit in a power MOS device by reducing the gate-source voltage 失效通过降低栅源电压降低功率MOS器件的自然电流限制
公开(公告)号：US5541799A
公开(公告)日：1996-07-30
申请号：US265609
申请日：1994-06-24
IPC分类号： H03K17/082 , H02H7/10
CPC分类号： H03K17/0822
摘要： In accordance with the present invention, an output current limit circuit for protecting a power MOS output device of an integrated circuit from an excessive drain current comprises a power MOS device 110, a means 30 to sense a predetermined trigger current, and a means 20 to reduce a gate-source voltage on MOS output device 110 to a predetermined approximately fixed value. A drain current I.sub.D flows through power MOS device 110 from output terminal 102 in response to the gate-source voltage. A short circuit condition may allow an excessive amount of drain current I.sub.D to flow through output terminal 102. The gate-source voltage is reduced in response to sensing the trigger current. Reducing the gate-source voltage raises a drain-source resistance of MOS device 110 and reduces drain current I.sub.D so that MOS device 110 is not damaged by the short circuit condition.
摘要翻译： 根据本发明，用于保护集成电路的功率MOS输出装置与过剩漏极电流的输出限流电路包括功率MOS器件110，感测预定触发电流的装置30和装置20至 将MOS输出装置110上的栅极 - 源极电压降低到预定的大致固定值。 漏极电流ID响应于栅极 - 源极电压从输出端子102流过功率MOS器件110。 短路状态可允许过量的漏极电流ID流过输出端子102.响应于感测触发电流，栅极 - 源极电压被降低。 降低栅极 - 源极电压会提高MOS器件110的漏极 - 源极电阻并且减少漏极电流ID，使得MOS器件110不会被短路状态损坏。
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公开(公告)号：US06373094B1
公开(公告)日：2002-04-16
申请号：US09908024
申请日：2001-07-18
IPC分类号： H01L29788
摘要： An EEPROM cell (10) formed on a substrate (18) using conventional process steps is provided. The cell (10) includes first (12) and second (14) conductive regions in the substrate (18) below the substrate's outer surface (28), and the first (12) and second (14) conductive regions are laterally displaced from one another by a predetermined distance (32). The cell (10) also includes an insulating layer (20) outwardly from the outer surface (28) of the substrate (18) positioned so that its edges are substantially in alignment between the first (12) and second (14) conductive regions. The cell (10) further includes a floating gate layer (22) outwardly from the insulating layer (20) and in substantially the same shape as the insulating layer (20). The cell (10) also includes a diffusion region (24 or 26) that extends laterally from at least one of the first (12) and second (14) conductive regions so as to overlap with the insulating layer (20). The diffusion region (24 or 26) provides a source of charge for placement on the floating gate layer (22) when programming the EEPROM cell (10).
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公开(公告)号：US5691940A
公开(公告)日：1997-11-25
申请号：US656553
申请日：1996-05-31
CPC分类号： G01R31/3004 , G06F1/30
摘要： A method and apparatus for programmable current limits is provided in which a plurality of current limit programmable cells (44 and 46) are programmed with a current limit. Output circuitry (14 and 16) which outputs current is limited by current limit circuitry (20, 24, 38, 40, and 42) when the output current reaches the programmed current limit.
摘要翻译： 提供了一种用于可编程电流限制的方法和装置，其中多个限流可编程单元（44和46）被编程为电流限制。 当输出电流达到编程电流极限时，输出电流的输出电路（14和16）受限流电路（20,24,38,40和42）限制。
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公开(公告)号：US09530555B2
公开(公告)日：2016-12-27
申请号：US13434807
申请日：2012-03-29
申请人： Ross E. Teggatz , Wayne T. Chen
发明人： Ross E. Teggatz , Wayne T. Chen
摘要： Wireless power transmittal apparatus and systems are disclosed in which transmitter and receiver inductors, or coils, are coupled in configurations for wirelessly transferring power and/or data among them. In preferred implementations, a plurality of non-coplanar primary side coils are provided in power transmittal apparatus for transmitting power, or power and data.
摘要翻译： 公开了无线电力传输装置和系统，其中发射机和接收机电感器或线圈以用于在它们之间无线传输功率和/或数据的配置耦合。 在优选实施方案中，在功率传输装置中提供多个非共面初级侧线圈，用于发射功率或功率和数据。
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公开(公告)号：US09343988B2
公开(公告)日：2016-05-17
申请号：US13567039
申请日：2012-08-04
CPC分类号： H02M3/33507 , H02M1/08 , H02M1/14 , H02M1/42 , H02M1/4225 , H02M3/3387 , H02M2001/0006 , H02M2001/0009 , H02M2001/0032 , H05B33/0815 , H05B33/0851 , Y02B70/126 , Y02B70/16
摘要： Circuits, systems, and methods of current mode regulation include a primary side for receiving an input signal and a secondary for outputting an output signal. A regulator spans the primary and secondary sides in a configuration by which the input signal may be rectified and thereafter provided to the output node as an output signal. A current monitor is provided at the output node for comparing the output signal to a reference. A communication link is included for providing feedback to the primary side of the regulator for use in regulating the signal.
摘要翻译： 电流模式调节的电路，系统和方法包括用于接收输入信号的初级侧和用于输出输出信号的次级。 调节器跨越主要和次要侧面，通过该配置可以对输入信号进行整流，此后将其提供给输出节点作为输出信号。 在输出节点处提供电流监视器，用于将输出信号与参考值进行比较。 包括通信链路，用于向调节器的初级侧提供反馈信号以用于调节信号。
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公开(公告)号：US20130062967A1
公开(公告)日：2013-03-14
申请号：US13616726
申请日：2012-09-14
IPC分类号： H01F38/14
摘要： A system for power transfer is provided. In one exemplary embodiment, the system includes an inductive power device, such as a device that transmits or receives power over an inductive coupling. For example, an adjustable impedance is coupled to the inductive power device, where the adjustable impedance is used for dynamically controlling the power gain in the inductive power device, such as by damping power generated by circuit impedances, such as inductances, capacitances or resistances, and combinations thereof.
摘要翻译： 提供电力传输系统。 在一个示例性实施例中，系统包括感应功率器件，例如通过感应耦合发送或接收功率的器件。 例如，可调阻抗耦合到感应功率器件，其中可调阻抗用于动态地控制感应功率器件中的功率增益，例如通过阻抗由电路阻抗（例如电感，电容或电阻）产生的功率， 及其组合。
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公开(公告)号：US20120087187A1
公开(公告)日：2012-04-12
申请号：US13327364
申请日：2011-12-15
申请人： Ross E. Teggatz , Wayne T. Chen , Brett Smith , Eric Blackall
发明人： Ross E. Teggatz , Wayne T. Chen , Brett Smith , Eric Blackall
CPC分类号： G11C16/10 , G11C16/0408 , G11C16/3468 , G11C27/005
摘要： The invention provides methods for programming a floating gate. A floating gate tunneling device is used with an analog comparing device in a circuit having a floating reference node and an offset-mitigating feedback loop for iteratively programming a floating gate, or multiple floating gates.
摘要翻译： 本发明提供了编程浮动栅极的方法。 在具有浮置参考节点和偏移减轻反馈环路的电路中使用浮动栅极隧道装置与模拟比较装置，用于迭代地编程浮动栅极或多个浮动栅极。
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