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1.发明申请Semiconductor Device Manufactured Using Passivation of Crystal Domain Interfaces in Hybrid Orientation Technology 审中-公开在混合定向技术中使用晶体界面钝化制造的半导体器件公开(公告)号：US20080128821A1
公开(公告)日：2008-06-05
申请号：US11566263
申请日：2006-12-04
IPC分类号： H01L29/04 , H01L21/8238
CPC分类号： H01L21/823807 , H01L27/092 , H01L29/045 , H01L29/7833
摘要： The invention provides, in one aspect, a method of forming a semiconductor device including providing a semiconductor substrate that comprises a first portion having a crystal orientation and a second portion located over the first portion and having a different crystal orientation. An interfacial region is located between the first portion and second portion. A passivating dopant is implanted into the interfacial region to passivate unterminated bonds within the interfacial region.
摘要翻译： 本发明在一个方面提供一种形成半导体器件的方法，该半导体器件包括提供包括具有晶体取向的第一部分和位于第一部分上方并具有不同晶体取向的第二部分的半导体衬底。 界面区域位于第一部分与第二部分之间。 将钝化掺杂剂注入界面区域以钝化界面区域内的未终止键。
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公开(公告)号：US20070072383A1
公开(公告)日：2007-03-29
申请号：US11558161
申请日：2006-11-09
IPC分类号： H01L21/331 , H01L23/52 , H01L21/8222 , H01L23/48 , H01L29/40 , H01L21/336
CPC分类号： H01L29/1054 , H01L29/165 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/66651
摘要： A method (10) of forming a transistor (100) includes treating (12) at least some of a semiconductor substrate (102) with carbon and then forming (18) a gate structure (114) over the semiconductor substrate. A channel region (122) is thereby being defined within the semiconductor substrate (102) below the gate structure (114). Source and drain regions (140, 142) are then formed (26) within the semiconductor substrate (102) on opposing sides of the channel (122) with a phosphorus dopant.
摘要翻译： 形成晶体管（100）的方法（10）包括用碳处理（12）半导体衬底（102）中的至少一些，然后在半导体衬底上形成（18）栅极结构（114）。 因此，沟道区域（122）被限定在栅极结构（114）下方的半导体衬底（102）内。 然后用磷掺杂剂在沟道（122）的相对侧上的半导体衬底（102）内在源极和漏极区（140,142）内形成（26）。
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3.发明申请Semiconductor device having optimized shallow junction geometries and method for fabrication thereof 有权具有优化的浅结几何形状的半导体器件及其制造方法公开(公告)号：US20050245021A1
公开(公告)日：2005-11-03
申请号：US10835121
申请日：2004-04-29
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L21/823864
摘要： The present invention provides, in one embodiment, a method of fabricating a semiconductor device (100). The method comprises growing an oxide layer (120) on a gate structure (114) and a substrate (102) and implanting a dopant (124) into the substrate (102) and the oxide layer (120). Implantation is such that a portion of the dopant (124) remains in the oxide layer (120) to form an implanted oxide layer (126). The method further includes depositing a protective oxide layer (132) on the implanted oxide layer (126) and forming etch-resistant off-set spacers (134). The etch-resistant off-set spacers (134) are formed adjacent sidewalls of the gate structure (114) and on the protective oxide layer (132). The etch resistant off-set spacers having an inner perimeter (135) adjacent the sidewalls and an opposing outer perimeter (136). The method also comprises removing portions of the protective oxide layer (132) lying outside the outer perimeter (136) of the etch-resistant off-set spacers (134). Other embodiments of the present invention include a transistor device (200) and method of manufacturing an integrated circuit (300).
摘要翻译： 本发明在一个实施例中提供一种制造半导体器件（100）的方法。 该方法包括在栅极结构（114）和衬底（102）上生长氧化物层（120）并将掺杂剂（124）注入到衬底（102）和氧化物层（120）中。 注入使得掺杂剂（124）的一部分保留在氧化物层（120）中以形成注入的氧化物层（126）。 该方法还包括在注入的氧化物层（126）上沉积保护性氧化物层（132）并且形成耐腐蚀的偏置间隔物（134）。 在栅极结构（114）的侧壁和保护氧化物层（132）上形成耐蚀刻偏置间隔物（134）。 耐腐蚀的偏置间隔件具有邻近侧壁的内周边（135）和相对的外周边（136）。 该方法还包括去除位于耐蚀刻偏移间隔物（134）的外周（136）外的保护氧化物层（132）的部分。 本发明的其他实施例包括晶体管器件（200）和制造集成电路（300）的方法。
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公开(公告)号：US07902576B2
公开(公告)日：2011-03-08
申请号：US11558161
申请日：2006-11-09
IPC分类号： H01L29/76
CPC分类号： H01L29/1054 , H01L29/165 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/66651
摘要： A method (10) of forming a transistor (100) includes treating (12) at least some of a semiconductor substrate (102) with carbon and then forming (18) a gate structure (114) over the semiconductor substrate. A channel region (122) is thereby being defined within the semiconductor substrate (102) below the gate structure (114). Source and drain regions (140, 142) are then formed (26) within the semiconductor substrate (102) on opposing sides of the channel (122) with a phosphorus dopant.
摘要翻译： 形成晶体管（100）的方法（10）包括用碳处理（12）半导体衬底（102）中的至少一些，然后在半导体衬底上形成（18）栅极结构（114）。 因此，沟道区域（122）被限定在栅极结构（114）下方的半导体衬底（102）内。 然后用磷掺杂剂在沟道（122）的相对侧上的半导体衬底（102）内在源极和漏极区（140,142）内形成（26）。
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公开(公告)号：US20060060893A1
公开(公告)日：2006-03-23
申请号：US10943278
申请日：2004-09-17
IPC分类号： H01L29/80
CPC分类号： H01L29/1054 , H01L29/165 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/66651
摘要： A method (10) of forming a transistor (100) includes treating (12) at least some of a semiconductor substrate (102) with carbon and then forming (18) a gate structure (114) over the semiconductor substrate. A channel region (122) is thereby being defined within the semiconductor substrate (102) below the gate structure (114). Source and drain regions (140, 142) are then formed (26) within the semiconductor substrate (102) on opposing sides of the channel (122) with a phosphorus dopant.
摘要翻译： 形成晶体管（100）的方法（10）包括用碳处理（12）半导体衬底（102）中的至少一些，然后在半导体衬底上形成（18）栅极结构（114）。 因此，沟道区域（122）被限定在栅极结构（114）下方的半导体衬底（102）内。 然后用磷掺杂剂在沟道（122）的相对侧上的半导体衬底（102）内在源极和漏极区（140,142）内形成（26）。
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公开(公告)号：US09048180B2
公开(公告)日：2015-06-02
申请号：US11383721
申请日：2006-05-16
IPC分类号： H01L21/02 , H01L21/265 , H01L21/318 , H01L21/324 , H01L29/66
CPC分类号： H01L21/26513 , H01L21/3185 , H01L21/324 , H01L29/6656 , H01L29/6659
摘要： A low stress sacrificial cap layer 120 having a silicon oxide liner film 130, a low stress silicon film 140, and a silicon nitride film Alternatively, a low stress sacrificial cap layer 410 having a silicon oxide liner film 130 and a graded silicon nitride film 420. Also, methods 300, 500 for fabricating a transistor 20, 400 having a low stress sacrificial cap layer 120, 410.
摘要翻译： 具有氧化硅衬垫膜130，低应力硅膜140和氮化硅膜的低应力牺牲帽层120或者，具有氧化硅衬垫膜130和梯度氮化硅膜420的低应力牺牲帽层410 而且，用于制造具有低应力牺牲帽层120,410的晶体管20,400的方法300,500。
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公开(公告)号：US20090170256A1
公开(公告)日：2009-07-02
申请号：US12206456
申请日：2008-09-08
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L21/268 , H01L21/2686 , H01L21/324 , H01L21/823807 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A method of forming a transistor comprising forming a gate structure over an n-type semiconductor body and forming recesses substantially aligned to the gate structure in the semiconductor body. Silicon germanium is then epitaxially grown in the recesses and a silicon cap layer is formed over the silicon germanium. Further introduction of impurities into the silicon germanium to increase the melting point thereof and implanting p-type source/drain regions in the semiconductor body is included in the method. The method concludes with performing a high temperature thermal treatment.
摘要翻译： 一种形成晶体管的方法，包括在n型半导体本体上形成栅极结构，并形成与半导体本体中的栅极结构基本对准的凹槽。 然后在凹槽中外延生长硅锗，并在硅锗上形成硅帽层。 在该方法中包括将杂质进一步引入硅锗以增加其熔点并在半导体本体中注入p型源/漏区。 该方法的结论是进行高温热处理。
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公开(公告)号：US20090045472A1
公开(公告)日：2009-02-19
申请号：US11837709
申请日：2007-08-13
申请人： Srinivasan Chakravarthi , Narendra Singh Mehta , Rajesh Khamankar , Ajith Varghese , Malcolm J. Bevan , Tad Grider
发明人： Srinivasan Chakravarthi , Narendra Singh Mehta , Rajesh Khamankar , Ajith Varghese , Malcolm J. Bevan , Tad Grider
IPC分类号： H01L29/94 , H01L21/8234
CPC分类号： H01L21/26506 , H01L21/2658 , H01L21/28035 , H01L21/28176 , H01L29/4916 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device includes source/drain regions formed in a substrate and having a concentration of nitrogen of at least about 5E18 cm−3. A gate dielectric is located over the substrate and between the source/drain regions. Gate sidewall spacers are located over said source/drain regions. A nitrogen-doped electrode including polysilicon is located over the gate dielectric. The electrode has a concentration of nitrogen therein greater than the concentration of nitrogen in the source/drain regions.
摘要翻译： 半导体器件包括形成在衬底中并具有至少约5E18cm-3的氮浓度的源极/漏极区域。 栅极电介质位于衬底上并且在源/漏区之间。 栅极侧壁间隔物位于所述源极/漏极区域之上。 包括多晶硅的氮掺杂电极位于栅极电介质上方。 电极的氮浓度大于源极/漏极区域中的氮浓度。
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公开(公告)号：US20080277699A1
公开(公告)日：2008-11-13
申请号：US11747708
申请日：2007-05-11
IPC分类号： H01L29/94 , H01L21/336
CPC分类号： H01L29/7848 , H01L21/3065 , H01L29/165 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7834
摘要： A PMOS transistor and a method for fabricating a PMOS transistor. The method may include providing a semiconductor wafer having a PMOS transistor gate stack, source/drain extension regions, and active regions. The method may also include forming epi sidewalls, performing a ex-situ recess etch, and performing an in-situ recess etch. The ex-situ recess etch and the in-situ recess etch form recessed active regions. The PMOS transistor is formed by a method using ex-situ and in-situ etch and has epitaxial SiGe regions with a greatest width at the surface of the semiconductor wafer.
摘要翻译： 一种PMOS晶体管及其制造方法。 该方法可以包括提供具有PMOS晶体管栅极叠层，源极/漏极延伸区域和有源区域的半导体晶片。 该方法还可以包括形成外壁侧壁，执行非原位凹槽蚀刻以及进行原位凹槽蚀刻。 原位凹槽蚀刻和原位凹陷蚀刻形成凹陷的有源区。 PMOS晶体管通过使用非原位和原位蚀刻的方法形成，并且具有在半导体晶片的表面处具有最大宽度的外延SiGe区域。
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公开(公告)号：US07112516B2
公开(公告)日：2006-09-26
申请号：US10677614
申请日：2003-10-02
IPC分类号： H01L21/22
CPC分类号： H01L21/2255
摘要： One aspect of the invention relates to a method of forming P-N junctions within a semiconductor substrate. The method involves providing a temporary impurity species, such as fluorine, within the semiconductor crystal matrix prior to solid source in-diffusion of the primary dopant, such as boron. The impurity atom is a faster diffusing species relative to silicon atoms. During in-diffusion, the temporary impurity species acts to reduce the depth to which the primary dopant diffuses and thereby facilitates the formation of very shallow junctions.
摘要翻译： 本发明的一个方面涉及一种在半导体衬底内形成P-N结的方法。 该方法包括在主要掺杂剂例如硼的固体源扩散之前在半导体晶体矩阵内提供临时杂质物质，例如氟。 杂质原子相对于硅原子是更快的扩散物质。 在扩散期间，临时杂质物质用于减小初级掺杂剂扩散的深度，从而有助于形成非常浅的结。
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