公开(公告)号：US20100271138A1

公开(公告)日：2010-10-28

申请号：US12428490

申请日：2009-04-23

申请人： Krishna Thakur ,  Deependra K. Jain ,  Vinod Jain

发明人： Krishna Thakur ,  Deependra K. Jain ,  Vinod Jain

IPC分类号： H03L7/00

CPC分类号： H03L7/099 ,  H03L7/0898 ,  H03L7/10 ,  H03L2207/06

摘要： A phase-locked loop (PLL) system generates an oscillator signal based on an input reference signal. A calibration circuit generates a calibration current, and a voltage-to-current converter converts a control voltage into a first current. A current-controlled oscillator generates the oscillator signal based on the first current and the calibration current. A charge pump circuit, which is connected to a phase detector, the voltage-to-current converter, and the calibration circuit, generates a charge pump current based on the first current and the calibration current. The charge pump current is used to generate the control voltage based on an error signal.

摘要翻译： 锁相环（PLL）系统基于输入参考信号产生振荡器信号。 校准电路产生校准电流，电压 - 电流转换器将控制电压转换成第一电流。 电流控制振荡器基于第一电流和校准电流产生振荡器信号。 连接到相位检测器，电压 - 电流转换器和校准电路的电荷泵电路基于第一电流和校准电流产生电荷泵电流。 电荷泵电流用于根据误差信号产生控制电压。

公开(公告)号：US09362894B1

公开(公告)日：2016-06-07

申请号：US14702776

申请日：2015-05-04

申请人： Ateet Omer ,  Deependra K. Jain ,  Anand Kumar Sinha ,  Krishna Thakur

发明人： Ateet Omer ,  Deependra K. Jain ,  Anand Kumar Sinha ,  Krishna Thakur

IPC分类号： H03K3/00 ,  H03K3/012 ,  H03K5/24 ,  H03K5/156

CPC分类号： H03K5/1565 ,  H03K5/19 ,  H03K5/24

摘要： A clock generator includes a diagnostic circuit that includes first and second muxes, first and second comparators, a logic gate, and a counter. The first mux receives first and second voltage signals and outputs a first intermediate signal based on a control signal. The second mux receives third and fourth voltage signals and outputs a second intermediate signal based on the control signal. The first and second comparators compare the intermediate signals with a first signal that is indicative of a DC value of the clock signal for generating first and second comparison signals. The logic gate receives the first and second intermediate signals and generates a control signal. The counter receives the clock signal and the control signal and generates a clock ready signal that is indicative of stability and quality of the clock signal.

摘要翻译： 时钟发生器包括包括第一和第二多路复用器的诊断电路，第一和第二比较器，逻辑门和计数器。 第一复用器接收第一和第二电压信号，并且基于控制信号输出第一中间信号。 第二复用器接收第三和第四电压信号，并且基于控制信号输出第二中间信号。 第一和第二比较器将中间信号与表示用于产生第一和第二比较信号的时钟信号的DC值的第一信号进行比较。 逻辑门接收第一和第二中间信号并产生控制信号。 计数器接收时钟信号和控制信号，并产生指示时钟信号的稳定性和质量的时钟就绪信号。

公开(公告)号：US09252791B1

公开(公告)日：2016-02-02

申请号：US14580136

申请日：2014-12-22

申请人： Anand Kumar Sinha ,  Deependra K. Jain ,  Krishna Thakur

发明人： Anand Kumar Sinha ,  Deependra K. Jain ,  Krishna Thakur

IPC分类号： H03L7/06 ,  H03L7/099

CPC分类号： H03L7/099 ,  H03L7/104 ,  H03L2207/06

摘要： A phase locked loop (PLL) system generates an oscillator signal by providing a fixed control voltage to a programmable voltage to current converter having switch selection inputs and a variable current output. Logic values are provided to the switch selection inputs to adjust a control current at the variable current output and a frequency of the oscillator signal is adjusted based on the control current. The logic values are fixed when a first condition is reached, which is based on the frequency of the oscillator signal, a division factor, and an input reference signal frequency. The fixed control voltage provided to the programmable voltage to current converter is then replaced with a charge pump control voltage based on an error signal. The error signal is based on a comparison of the input reference signal frequency and a fraction of the oscillating frequency.

摘要翻译： 锁相环（PLL）系统通过向具有开关选择输入和可​​变电流输出的可编程电压到电流转换器提供固定的控制电压来产生振荡器信号。 将逻辑值提供给开关选择输入，以调整可变电流输出端的控制电流，并根据控制电流调整振荡器信号的频率。 当达到基于振荡器信号的频率，分频因子和输入参考信号频率的第一条件时，逻辑值是固定的。 然后，提供给可编程电压到电流转换器的固定控制电压由基于误差信号的电荷泵控制电压代替。 误差信号基于输入参考信号频率和振荡频率的一小部分的比较。

公开(公告)号：US08378725B2

公开(公告)日：2013-02-19

申请号：US13046789

申请日：2011-03-14

申请人： Krishna Thakur ,  Deependra K. Jain ,  Vinod K. Jain

发明人： Krishna Thakur ,  Deependra K. Jain ,  Vinod K. Jain

IPC分类号： H03L7/06

CPC分类号： H03L7/0891

摘要： A phase-locked loop (PLL) generates an oscillator signal based on an input reference signal. A voltage-to-current converter converts a control voltage to a first current. A current-controlled oscillator generates the oscillator signal based on the first current. A dual charge pump circuit generates first and second charge pump currents having a predetermined ratio, based on a second current generated by a current mirror circuit and an error (feedback) signal. An active loop filter generates the control voltage based on the first and second charge pump currents. The active loop filter includes an input capacitance that varies with a variation in the predetermined ratio of the charge pump currents. The active loop filter also includes a transconductance stage having a transconductance that varies based on a third current generated by a current mirror circuit. The PLL bandwidth is independent of PVT variations and dependent only on the frequency of the input reference signal. In addition, the size of the input capacitor is relatively small so that the circuit requires very little space.

摘要翻译： 锁相环（PLL）基于输入参考信号产生振荡器信号。 电压 - 电流转换器将控制电压转换为第一电流。 电流控制振荡器基于第一电流产生振荡器信号。 双电荷泵电路基于由电流镜电路和误差（反馈）信号产生的第二电流产生具有预定比率的第一和第二电荷泵电流。 有源环路滤波器基于第一和第二电荷泵电流产生控制电压。 有源环路滤波器包括随着电荷泵电流的预定比率的变化而变化的输入电容。 有源环路滤波器还包括具有根据由电流镜电路产生的第三电流而变化的跨导的跨导级。 PLL带宽与PVT变化无关，仅取决于输入参考信号的频率。 此外，输入电容器的尺寸相对较小，使得电路需要非常小的空间。

公开(公告)号：US20110215842A1

公开(公告)日：2011-09-08

申请号：US12715396

申请日：2010-03-02

申请人： Ankesh Jain ,  Deependra K. Jain ,  Krishna Thakur

发明人： Ankesh Jain ,  Deependra K. Jain ,  Krishna Thakur

IPC分类号： H03K21/00

CPC分类号： H03K21/00

摘要： A programmable digital clock signal frequency divider module has a module clock input, module clock output, a scaling factor input, two programming inputs, and a tertiary input. A primary divider module with a primary divider module output and a clock input are coupled to the module clock input. A secondary divider module includes a multiplexer and a divide by two latch with a latch clock input coupled to the primary divider module output. In operation, logic values applied to the scaling factor input, and the programming inputs, result in the primary divider module processing a first sequence of cycles of a primary digital clock signal into a first base clock signal and processing a subsequent second sequence of cycles into a second base clock signal. The first base clock signal and the second base clock signal provide a sequence of clock pulses to the secondary divider module. Edges of the sequence of clock pulses trigger the divide by two latch, which results in a latch output clock signal with a 50% duty cycle at the output of the divide by two latch. Logic values at the tertiary input select either the sequence of clock pulses or the latch output clock signal to be a module clock output signal at the module clock output.

摘要翻译： 可编程数字时钟信号分频器模块具有模块时钟输入，模块时钟输出，缩放因子输入，两个编程输入和三次输入。 具有主分频器模块输出和时钟输入的主分频器模块耦合到模块时钟输入。 次分频器模块包括多路复用器和由两个锁存器除以锁存时钟输入，耦合到主分频器模块输出。 在操作中，应用于缩放因子输入和编程输入的逻辑值导致主分配器模块将主数字时钟信号的第一序列周期处理为第一基本时钟信号并且处理后续的第二次循环序列 第二基本时钟信号。 第一基本时钟信号和第二基本时钟信号向次级分频器模块提供时钟脉冲序列。 时钟脉冲序列的边沿触发了两个锁存器的分频，这导致锁存输出时钟信号在分频输出端有两个锁存器，占空比为50％。 第三输入的逻辑值选择时钟脉冲序列或锁存器输出时钟信号，作为模块时钟输出端的模块时钟输出信号。

公开(公告)号：US09331698B2

公开(公告)日：2016-05-03

申请号：US14146721

申请日：2014-01-02

申请人： Deependra K. Jain ,  Krishna Thakur

发明人： Deependra K. Jain ,  Krishna Thakur

IPC分类号： H03L7/06 ,  H03K19/0175 ,  H03L7/085 ,  H03K5/156 ,  H03L7/099

CPC分类号： H03K19/017509 ,  H03K5/1565 ,  H03L7/085 ,  H03L7/0995

摘要： A level shifter circuit for level shifting voltages of signals crossing multiple circuit domains includes an input stage and a driver stage. The input stage receives an oscillating signal generated by a ring oscillator and generates an inverted oscillating signal. The differential oscillating signals are provided to the driver stage, which level shifts a voltage level of the oscillating signal to a level of a supply voltage of the ring oscillator.

摘要翻译： 用于跨越多个电路域的信号的电平移位电压的电平移位器电路包括输入级和驱动级。 输入级接收由环形振荡器产生的振荡信号，并产生反相振荡信号。 差分振荡信号被提供给驱动级，该电平将振荡信号的电压电平移动到环形振荡器的电源电压的电平。

公开(公告)号：US20150188543A1

公开(公告)日：2015-07-02

申请号：US14146721

申请日：2014-01-02

申请人： Deependra K. Jain ,  Krishna Thakur

发明人： Deependra K. Jain ,  Krishna Thakur

IPC分类号： H03K19/0175 ,  H03K5/156 ,  H03L7/099 ,  H03L7/085

CPC分类号： H03K19/017509 ,  H03K5/1565 ,  H03L7/085 ,  H03L7/0995

摘要： A level shifter circuit for level shifting voltages of signals crossing multiple circuit domains includes an input stage and a driver stage. The input stage receives an oscillating signal generated by a ring oscillator and generates an inverted oscillating signal. The differential oscillating signals are provided to the driver stage, which level shifts a voltage level of the oscillating signal to a level of a supply voltage of the ring oscillator.

摘要翻译： 用于跨越多个电路域的信号的电平移位电压的电平移位器电路包括输入级和驱动级。 输入级接收由环形振荡器产生的振荡信号，并产生反相振荡信号。 差分振荡信号被提供给驱动级，该电平将振荡信号的电压电平移动到环形振荡器的电源电压的电平。

公开(公告)号：US08248130B2

公开(公告)日：2012-08-21

申请号：US12786496

申请日：2010-05-25

申请人： Vinod Jain ,  Deependra K. Jain ,  Krishna Thakur ,  Avinish Chandra Tripathi ,  Sanjay Kumar Wadhwa

发明人： Vinod Jain ,  Deependra K. Jain ,  Krishna Thakur ,  Avinish Chandra Tripathi ,  Sanjay Kumar Wadhwa

IPC分类号： H03K3/17 ,  H03K5/04 ,  H03K7/08

CPC分类号： H03K5/1565

摘要： A duty cycle correction circuit for correcting the duty cycle of a clock signal generated by a clock generator includes a complementary buffer chain, level shifter circuits and a self-bias circuit. A clock signal with a distorted duty cycle and its complement are provided to the level shifter circuits. The level shifter circuits reduce the magnitude of voltage of the clock signal and the complement and generate level shifted signals. The level shifted signals are provided to a differential amplifier that generates a control signal indicating the magnitude of distortion in the duty cycle. The control signal is used to correct the duty cycle of the clock signal. The self-bias circuit is used to bias the differential amplifier.

摘要翻译： 用于校正由时钟发生器产生的时钟信号的占空比的占空比校正电路包括互补缓冲链，电平移位器电路和自偏置电路。 具有失真占空比的时钟信号及其补码提供给电平移位器电路。 电平移位器电路减小时钟信号和补码的电压幅值，并产生电平移位信号。 电平移位信号被提供给差分放大器，该差分放大器产生指示占空比中的失真幅度的控制信号。 控制信号用于校正时钟信号的占空比。 自偏置电路用于偏置差分放大器。

公开(公告)号：US20110291724A1

公开(公告)日：2011-12-01

申请号：US12786496

申请日：2010-05-25

申请人： Vinod Jain ,  Deependra K. Jain ,  Krishna Thakur ,  Avinash Chandra Tripathi ,  Sanjay Kumar Wadhwa

发明人： Vinod Jain ,  Deependra K. Jain ,  Krishna Thakur ,  Avinash Chandra Tripathi ,  Sanjay Kumar Wadhwa

IPC分类号： H03K3/017

CPC分类号： H03K5/1565

摘要： A duty cycle correction circuit for correcting the duty cycle of a clock signal generated by a clock generator includes a complementary buffer chain, level shifter circuits and a self-bias circuit. A clock signal with a distorted duty cycle and its complement are provided to the level shifter circuits. The level shifter circuits reduce the magnitude of voltage of the clock signal and the complement and generate level shifted signals. The level shifted signals are provided to a differential amplifier that generates a control signal indicating the magnitude of distortion in the duty cycle. The control signal is used to correct the duty cycle of the clock signal. The self-bias circuit is used to bias the differential amplifier.

摘要翻译： 用于校正由时钟发生器产生的时钟信号的占空比的占空比校正电路包括互补缓冲链，电平移位器电路和自偏置电路。 具有失真占空比的时钟信号及其补码提供给电平移位器电路。 电平移位器电路减小时钟信号和补码的电压幅值，并产生电平移位信号。 电平移位信号被提供给差分放大器，该差分放大器产生指示占空比中的失真幅度的控制信号。 控制信号用于校正时钟信号的占空比。 自偏置电路用于偏置差分放大器。

公开(公告)号：US08350631B1

公开(公告)日：2013-01-08

申请号：US13159440

申请日：2011-06-14

申请人： Sanjay K. Wadhwa ,  Deependra K. Jain

发明人： Sanjay K. Wadhwa ,  Deependra K. Jain

IPC分类号： H03K3/02

CPC分类号： H03K3/0231 ,  H03K4/502

摘要： A relaxation oscillator for generating oscillator signal includes a ramp voltage generating circuit, a reference voltage generating circuit, a reference voltage switching circuit, and a digital logic circuit. The reference voltage generating circuit generates one or more reference voltages and the ramp voltage generating circuit generates one or more ramp voltages. The ramp voltages are compared with each of the reference voltages by sequentially switching the reference voltages using a reference voltage switching signal generated by the reference voltage switching circuit. The oscillator signal is generated by the digital logic circuit based on the results of the comparisons.

摘要翻译： 用于产生振荡器信号的张弛振荡器包括斜坡电压产生电路，参考电压产生电路，参考电压切换电路和数字逻辑电路。 参考电压产生电路产生一个或多个参考电压，斜坡电压产生电路产生一个或多个斜坡电压。 通过使用由参考电压切换电路产生的参考电压切换信号顺序切换参考电压，将斜坡电压与每个参考电压进行比较。 振荡器信号由数字逻辑电路根据比较结果产生。