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1.发明申请UTILIZATION-AWARE LOW-OVERHEAD LINK-WIDTH MODULATION FOR POWER REDUCTION IN INTERCONNECTS 有权用于互连中功率降低的应用 - 低电平连接宽度调节公开(公告)号：US20140006673A1
公开(公告)日：2014-01-02
申请号：US13536852
申请日：2012-06-28
申请人： Ankush Varma , Buck W. Gremel , Robert G. Blankenship , Krishnakanth V. Sistla , Michael F. Cole
发明人： Ankush Varma , Buck W. Gremel , Robert G. Blankenship , Krishnakanth V. Sistla , Michael F. Cole
IPC分类号： G06F13/40
CPC分类号： G06F13/4027 , G06F1/3203 , G06F1/3253 , G06F13/4018 , G06F13/4221 , G06F15/16 , Y02D10/151
摘要： Methods and apparatus relating to low-overhead utilization-aware link-width modulation to reduce power consumption in interconnects are described. In one embodiment, a link width modulation logic adjusts the width of an interconnect link. More particularly, the link width modulation logic causes the interconnect link to transition from a first width to a second width based on comparison of a utilization value associated with the interconnect link against at least one of a plurality of utilization threshold values. Other embodiments are also disclosed and claimed.
摘要翻译： 描述了与低开销利用感知链路宽度调制相关的方法和装置，以减少互连中的功耗。 在一个实施例中，链路宽度调制逻辑调整互连链路的宽度。 更具体地，链路宽度调制逻辑使得互连链路基于与互连链路相关联的利用值与多个利用阈值中的至少一个的比较从第一宽度转换到第二宽度。 还公开并要求保护其他实施例。
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2.发明授权Utilization-aware low-overhead link-width modulation for power reduction in interconnects 有权利用率低的架空链路宽度调制，用于互连中的功率降低公开(公告)号：US09053244B2
公开(公告)日：2015-06-09
申请号：US13536852
申请日：2012-06-28
申请人： Ankush Varma , Buck W. Gremel , Robert G. Blankenship , Krishnakanth V. Sistla , Michael F. Cole
发明人： Ankush Varma , Buck W. Gremel , Robert G. Blankenship , Krishnakanth V. Sistla , Michael F. Cole
CPC分类号： G06F13/4027 , G06F1/3203 , G06F1/3253 , G06F13/4018 , G06F13/4221 , G06F15/16 , Y02D10/151
摘要： Methods and apparatus relating to low-overhead utilization-aware link-width modulation to reduce power consumption in interconnects are described. In one embodiment, a link width modulation logic adjusts the width of an interconnect link. More particularly, the link width modulation logic causes the interconnect link to transition from a first width to a second width based on comparison of a utilization value associated with the interconnect link against at least one of a plurality of utilization threshold values. Other embodiments are also disclosed and claimed.
摘要翻译： 描述了与低开销利用感知链路宽度调制相关的方法和装置，以减少互连中的功耗。 在一个实施例中，链路宽度调制逻辑调整互连链路的宽度。 更具体地，链路宽度调制逻辑使得互连链路基于与互连链路相关联的利用值与多个利用阈值中的至少一个的比较从第一宽度转换到第二宽度。 还公开并要求保护其他实施例。
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3.发明授权Method, apparatus, and a system for dynamically configuring a prefetcher based on a thread specific latency metric 有权方法，装置和用于基于线程特定的等待时间度量动态配置预取器的系统公开(公告)号：US08079031B2
公开(公告)日：2011-12-13
申请号：US11256536
申请日：2005-10-21
IPC分类号： G06F9/46
CPC分类号： G06F9/3851 , G06F9/383 , G06F12/0862 , G06F2212/502
摘要： A discussion of a dynamic configuration for a prefetcher is proposed. For example, a thread specific latency metric is calculated and provides dynamic feedback to the software on a per thread basis via the configuration and status registers. Likewise, the software can optionally use the information from the registers to dynamically configure the prefetching behavior and allows the software to be able to both query the performance and configure the prefetcher.
摘要翻译： 提出了对预取器的动态配置的讨论。 例如，计算线程特定的延迟度量，并通过配置和状态寄存器在每个线程的基础上向软件提供动态反馈。 同样，软件可以选择使用来自寄存器的信息来动态地配置预取行为，并允许软件能够查询性能并配置预取器。
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4.发明授权Method for utilizing a single multiplex address bus between DRAM, SRAM and ROM 失效在DRAM，SRAM和ROM之间利用单个复用地址总线的方法
公开(公告)号：US5901298A
公开(公告)日：1999-05-04
申请号：US726700
申请日：1996-10-07
CPC分类号： G06F13/4243
摘要： A memory interface device for interfacing between the local bus and a memory bus. The memory bus is coupled to a static memory and a dynamic memory. The interface device includes first and second internal buses coupled to a selecting device. The selecting device selectively couples one of the first and second internal buses to the memory bus. The memory interface device further includes an interface control unit having an input coupled to the local bus for receiving address and control signals. The interface control unit further has an output, coupled to the first internal bus for generating gating each data transfer in the burst in response to the address and control signals.
摘要翻译： 用于在本地总线和存储器总线之间进行接口的存储器接口装置。 存储器总线耦合到静态存储器和动态存储器。 接口设备包括耦合到选择设备的第一和第二内部总线。 选择装置将第一和第二内部总线中的一个选择性地耦合到存储器总线。 存储器接口设备还包括接口控制单元，其具有耦合到本地总线的输入，用于接收地址和控制信号。 接口控制单元还具有耦合到第一内部总线的输出，用于响应于地址和控制信号而在脉冲串中产生门控每个数据传输。
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