公开(公告)号：US08053325B1

公开(公告)日：2011-11-08

申请号：US12782320

申请日：2010-05-18

申请人： Anthony Chou ,  Arvind Kumar ,  Shreesh Narasimha

发明人： Anthony Chou ,  Arvind Kumar ,  Shreesh Narasimha

IPC分类号： H01L21/336

CPC分类号： H01L29/78615 ,  H01L29/66772

摘要： A body contact structure which reduce parasitic capacitance and improves body resistance of a device and methods of manufacture. The method includes forming a gate insulator material and gate electrode material on a substrate. The method further includes patterning the gate insulator material and the gate electrode material to form a gate structure having a shape with a first portion isolated from a second portion. The method further includes forming source and drain regions on sides of the first portion and a body contact at a side and under an area of the second portion, and forming an interlevel dielectric within a space that isolates the first portion from the second portion of the gate structure, and over the gate structure, source and drain regions and the body contact.

摘要翻译： 减少寄生电容并改善器件的体电阻和制造方法的体接触结构。 该方法包括在基板上形成栅极绝缘体材料和栅电极材料。 该方法还包括图案化栅极绝缘体材料和栅电极材料以形成具有与第二部分隔离的第一部分的形状的栅极结构。 该方法还包括在第一部分的侧面上形成源极和漏极区域，在第二部分的侧面和下面区域形成体接触，以及在隔离第一部分与第二部分的第二部分的空间内形成层间电介质 栅极结构，以及栅极结构，源极和漏极区域以及身体接触。

公开(公告)号：US20070010050A1

公开(公告)日：2007-01-11

申请号：US11160700

申请日：2005-07-06

申请人： Anthony Chou ,  Shreesh Narasimha

发明人： Anthony Chou ,  Shreesh Narasimha

IPC分类号： H01L21/8234

CPC分类号： H01L21/28176 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7833

摘要： The present invention provides methods for forming semiconductor FET devices having reduced gate edge leakage current by using plasma or thermal nitridation and low-temperature plasma re-oxidation processes post gate etch.

摘要翻译： 本发明提供了通过使用栅极蚀刻后的等离子体或热氮化和低温等离子体再氧化工艺形成具有减小的栅极边缘漏电流的半导体FET器件的方法。

公开(公告)号：US09184301B2

公开(公告)日：2015-11-10

申请号：US13600598

申请日：2012-08-31

申请人： Sarunya Bangsaruntip ,  Guy M. Cohen ,  Shreesh Narasimha ,  Jeffrey W. Sleight

发明人： Sarunya Bangsaruntip ,  Guy M. Cohen ,  Shreesh Narasimha ,  Jeffrey W. Sleight

IPC分类号： H01L29/66 ,  H01L29/786 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/423

CPC分类号： H01L29/78696 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/66772

摘要： An integrated circuit includes a plurality of gate-all-around (GAA) nanowire field effect transistors (FETs), a plurality of omega-gate nanowire FETs, and a plurality of planar channel FETs, wherein the plurality of GAA FETs, the plurality of omega-gate nanowire FETs, and the plurality of planar channel FETs are disposed on a single wafer.

摘要翻译： 集成电路包括多个栅极全能（GAA）纳米线场效应晶体管（FET），多个Ω-栅极纳米线FET和多个平面沟道FET，其中多个GAA FET，多个 ω-门纳米线FET，并且多个平面沟道FET设置在单个晶片上。

公开(公告)号：US20130221328A1

公开(公告)日：2013-08-29

申请号：US13405732

申请日：2012-02-27

申请人： Jeffrey W. Sleight ,  Josephine B. Chang ,  Isaac Lauer ,  Shreesh Narasimha

发明人： Jeffrey W. Sleight ,  Josephine B. Chang ,  Isaac Lauer ,  Shreesh Narasimha

IPC分类号： H01L29/775 ,  H01L21/335

CPC分类号： H01L29/66477 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696 ,  Y10S977/762

摘要： A method for forming a nanowire field effect transistor (FET) device, the method includes forming a suspended nanowire over a semiconductor substrate, forming a gate structure around a portion of the nanowire, forming a protective spacer adjacent to sidewalls of the gate and around portions of nanowire extending from the gate, removing exposed portions of the nanowire left unprotected by the spacer structure, and epitaxially growing a doped semiconductor material on exposed cross sections of the nanowire to form a source region and a drain region.

摘要翻译： 一种用于形成纳米线场效应晶体管（FET）器件的方法，该方法包括在半导体衬底上形成悬浮的纳米线，在纳米线的一部分周围形成栅极结构，形成邻近栅极的侧壁和周围部分的保护隔离层 的纳米线从栅极延伸，去除未被间隔物结构保护的纳米线的暴露部分，以及在纳米线的暴露的横截面上外延生长掺杂的半导体材料，以形成源极区域和漏极区域。

公开(公告)号：US20120319084A1

公开(公告)日：2012-12-20

申请号：US13600598

申请日：2012-08-31

申请人： Sarunya Bangsaruntip ,  Guy M. Cohen ,  Shreesh Narasimha ,  Jeffrey W. Sleight

发明人： Sarunya Bangsaruntip ,  Guy M. Cohen ,  Shreesh Narasimha ,  Jeffrey W. Sleight

IPC分类号： H01L27/088

CPC分类号： H01L29/78696 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/66772

摘要： An integrated circuit includes a plurality of gate-all-around (GAA) nanowire field effect transistors (FETs), a plurality of omega-gate nanowire FETs, and a plurality of planar channel FETs, wherein the plurality of GAA FETs, the plurality of omega-gate nanowire FETs, and the plurality of planar channel FETs are disposed on a single wafer.

摘要翻译： 集成电路包括多个栅极全能（GAA）纳米线场效应晶体管（FET），多个Ω-栅极纳米线FET和多个平面沟道FET，其中多个GAA FET，多个 ω-门纳米线FET，并且多个平面沟道FET设置在单个晶片上。

公开(公告)号：US08232599B2

公开(公告)日：2012-07-31

申请号：US12683456

申请日：2010-01-07

申请人： Anthony I. Chou ,  Arvind Kumar ,  Shreesh Narasimha ,  Ning Su ,  Huiling Shang

发明人： Anthony I. Chou ,  Arvind Kumar ,  Shreesh Narasimha ,  Ning Su ,  Huiling Shang

IPC分类号： H01L27/12 ,  H01L21/86

CPC分类号： H01L27/1207 ,  H01L21/84

摘要： An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.

摘要翻译： 提供了一种集成电路，其将同一芯片上的体FET和SOI FET集成在一起，其中，本体FET包括在大块衬底上形成的栅极氧化物上的栅极导体，其中本体FET的栅极电介质具有相同的厚度， 与SOI FET的掩埋绝缘层基本共面。 在优选实施例中，通过在指定的大容量器件区域中与SOI层的有源区相邻的SOI层和SOI晶片的掩埋绝缘层形成体接触沟槽，从SOI晶片形成本体FET。 邻近体接触沟槽的SOI层的有源区域形成体FET的栅极导体，其覆盖形成本体FET的栅极电介质的下层掩埋绝缘层的一部分。

公开(公告)号：US20120187492A1

公开(公告)日：2012-07-26

申请号：US13425681

申请日：2012-03-21

申请人： Anthony I. Chou ,  Arvind Kumar ,  Shreesh Narasimha ,  Ning Su ,  Huiling Shang

发明人： Anthony I. Chou ,  Arvind Kumar ,  Shreesh Narasimha ,  Ning Su ,  Huiling Shang

IPC分类号： H01L27/088

CPC分类号： H01L27/1207 ,  H01L21/84

摘要： An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.

摘要翻译： 提供了一种集成电路，其将同一芯片上的体FET和SOI FET集成在一起，其中，本体FET包括在大块衬底上形成的栅极氧化物上的栅极导体，其中本体FET的栅极电介质具有相同的厚度， 与SOI FET的掩埋绝缘层基本共面。 在优选实施例中，通过在指定的大容量器件区域中与SOI层的有源区相邻的SOI层和SOI晶片的掩埋绝缘层形成体接触沟槽，从SOI晶片形成本体FET。 邻近体接触沟槽的SOI层的有源区域形成体FET的栅极导体，其覆盖形成本体FET的栅极电介质的下层掩埋绝缘层的一部分。

公开(公告)号：US20120180010A1

公开(公告)日：2012-07-12

申请号：US13421400

申请日：2012-03-15

申请人： Anthony G. DOMENICUCCI ,  Terence L. Kane ,  Shreesh Narasimha ,  Karen A. Nummy ,  Viorel Ontalus ,  Yun-Yu Wang

发明人： Anthony G. DOMENICUCCI ,  Terence L. Kane ,  Shreesh Narasimha ,  Karen A. Nummy ,  Viorel Ontalus ,  Yun-Yu Wang

IPC分类号： G06F17/50

CPC分类号： H01L21/324 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7847

摘要： A method of fabricating a device using a sequence of annealing processes is provided. More particularly, a logic NFET device fabricated using a low temperature anneal to eliminate dislocation defects, method of fabricating the NFET device and design structure is shown and described. The method includes forming a stress liner over a gate structure and subjecting the gate structure and stress liner to a low temperature anneal process to form a stacking force in single crystalline silicon near the gate structure as a way to memorized the stress effort. The method further includes stripping the stress liner from the gate structure and performing an activation anneal at high temperature on device.

摘要翻译： 提供了使用退火处理序列制造器件的方法。 更具体地，示出并描述了使用低温退火制造以消除位错缺陷的逻辑NFET器件，制造NFET器件的方法和设计结构。 该方法包括在栅极结构上形成应力衬垫，并对栅极结构和应力衬垫进行低温退火处理，以在栅极结构附近的单晶硅中形成堆叠力，作为记忆应力的方法。 该方法还包括从栅极结构剥离应力衬垫并在器件上在高温下进行激活退火。

公开(公告)号：US20110225562A1

公开(公告)日：2011-09-15

申请号：US13100584

申请日：2011-05-04

申请人： Dureseti Chidambarrao ,  Gerald M. Davidson ,  Paul A. Hyde ,  Judith H. McCullen ,  Shreesh Narasimha

发明人： Dureseti Chidambarrao ,  Gerald M. Davidson ,  Paul A. Hyde ,  Judith H. McCullen ,  Shreesh Narasimha

IPC分类号： G06F9/455

CPC分类号： G06F17/5036

摘要： A method and computer program product for modeling a semiconductor transistor device structure having an active device area, a gate structure, and including a conductive line feature connected to the gate structure and disposed above the active device area, the conductive line feature including a conductive landing pad feature disposed near an edge of the active device area in a circuit to be modeled. The method includes determining a distance between an edge defined by the landing pad feature to an edge of the active device area, and, from modeling a lithographic rounding effect of the landing pad feature, determining changes in width of the active device area as a function of the distance between an edge defined by the landing pad feature to an edge of the active device area. From these data, an effective change in active device area width (deltaW adder) is related to the determined distance. Then, transistor model parameter values in a transistor compact model are updated for the transistor device to include deltaW adder values to be added to a built-in deltaW value. A netlist used in a device simulation may then include the deltaW adder values to quantify the influence of the lithographic rounding effect of the landing pad feature.

摘要翻译： 一种用于对具有有源器件区域，栅极结构并且包括连接到栅极结构并且设置在有源器件区域上方的导线特征来建模半导体晶体管器件结构的方法和计算机程序产品，所述导电线特征包括导电层 衬垫特征设置在待建模的电路中的有源器件区域的边缘附近。 该方法包括确定由着陆焊盘特征限定的边缘与有源器件区域的边缘之间的距离，以及通过建模着陆焊盘特征的光刻圆整效应，确定作为功能的有源器件区域的宽度变化 由着陆垫特征限定的边缘到活动设备区域的边缘之间的距离。 根据这些数据，有源器件区域宽度（deltaW加法器）的有效变化与确定的距离有关。 然后，晶体管紧凑型模型中的晶体管模型参数值被更新为晶体管器件，以包括要添加到内置deltaW值的ΔW加法器值。 在设备仿真中使用的网表可以包括deltaW加法器值，以量化着陆垫特征的光刻舍入效应的影响。

公开(公告)号：US08017483B2

公开(公告)日：2011-09-13

申请号：US12493549

申请日：2009-06-29

申请人： Gregory G. Freeman ,  Shreesh Narasimha ,  Ning Su ,  Hasan M. Nayfeh ,  Nivo Rovedo ,  Werner A. Rausch ,  Jian Yu

发明人： Gregory G. Freeman ,  Shreesh Narasimha ,  Ning Su ,  Hasan M. Nayfeh ,  Nivo Rovedo ,  Werner A. Rausch ,  Jian Yu

IPC分类号： H01L21/336

CPC分类号： H01L21/823425 ,  H01L21/26586 ,  H01L21/823412 ,  H01L29/66492 ,  H01L29/66659

摘要： The present invention provides a method of forming asymmetric field-effect-transistors. The method includes forming at least a first and a second gate-mask stack on top of a semiconductor substrate, wherein the first and second gate-mask stacks include at least, respectively, a first and a second gate conductor of a first and a second transistor and have, respectively, a top surface, a first side, and a second side with the second side being opposite to the first side; performing a first halo implantation from the first side of the first and second gate-mask stacks at a first angle while applying the first gate-mask stack in preventing the first halo implantation from reaching a first source/drain region of the second transistor, wherein the first angle is equal to or larger than a predetermined value; and performing a second halo implantation from the second side of the first and second gate-mask stacks at a second angle, thereby creating halo implant in a second source/drain region of the second transistor, wherein the first and second angles are measured against a normal to the substrate.

摘要翻译： 本发明提供了形成非对称场效应晶体管的方法。 该方法包括在半导体衬底的顶部上形成至少第一和第二栅极掩模叠层，其中第一和第二栅极掩模叠层至少分别包括第一和第二栅极掩模叠层的第一和第二栅极导体 分别具有顶表面，第一侧和第二侧，第二侧与第一侧相对; 以第一角度从第一和第二栅极掩模叠层的第一侧进行第一光晕注入，同时施加第一栅极掩模叠层以防止第一光晕注入到达第二晶体管的第一源极/漏极区域，其中 第一角度等于或大于预定值; 以及以第二角度从所述第一和第二栅极掩模叠层的第二侧执行第二光晕注入，从而在所述第二晶体管的第二源极/漏极区域中产生晕轮注入，其中所述第一和第二角度是针对 与基底垂直。