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    Method and system for forming dual work function gate electrodes in a semiconductor device
    2.
    发明授权
    Method and system for forming dual work function gate electrodes in a semiconductor device 有权
    在半导体器件中形成双功函数栅电极的方法和系统

    公开(公告)号：US07432566B2

    公开(公告)日：2008-10-07

    申请号：US10911165

    申请日：2004-08-04

    申请人： Antonio L. P. Rotondaro ,  Mark R. Visokay

    发明人： Antonio L. P. Rotondaro ,  Mark R. Visokay

    IPC分类号： H01L29/76

    CPC分类号： H01L21/28194 ,  H01L21/2807 ,  H01L21/28079 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/51 ,  H01L29/518

    摘要： A method is provided for forming dual work function gate electrodes. A dielectric layer is provided outwardly of a substrate. A metal layer is formed outwardly of the dielectric layer. A silicon-germanium layer is formed outwardly of the metal layer. A first portion of the silicon-germanium layer is removed to expose a first portion of the metal layer, with a second portion of the silicon-germanium layer remaining over a second portion of the metal layer. A silicon-germanium metal compound layer is formed from the second portion of the silicon-germanium layer and the second portion of the metal layer. A first gate electrode comprising the first portion of the metal layer is formed. A second gate electrode comprising the silicon-germanium metal compound layer is formed.

    摘要翻译： 提供了一种用于形成双功函数栅电极的方法。 介电层设置在基板的外侧。 在电介质层的外侧形成金属层。 在金属层的外部形成硅锗层。 去除硅 - 锗层的第一部分以暴露金属层的第一部分，硅 - 锗层的第二部分保留在金属层的第二部分上。 硅 - 锗金属化合物层由硅 - 锗层的第二部分和金属层的第二部分形成。 形成包括金属层的第一部分的第一栅电极。 形成包含硅 - 锗金属化合物层的第二栅电极。

    Method to selectively recess ETCH regions on a wafer surface using capoly as a mask
    5.
    发明授权
    Method to selectively recess ETCH regions on a wafer surface using capoly as a mask 有权
    使用capoly作为掩模来选择性地在晶片表面上凹入ETCH区域的方法

    公开(公告)号：US07169659B2

    公开(公告)日：2007-01-30

    申请号：US10931195

    申请日：2004-08-31

    申请人： Antonio L. P. Rotondaro ,  Seetharaman Sridhar

    发明人： Antonio L. P. Rotondaro ,  Seetharaman Sridhar

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/7843 ,  H01L29/7848

    摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply strain to channel regions of devices while mitigating masking operations employed. A CAPOLY layer is formed over an NMOS region of a semiconductor device (102). A recess etch is performed on active regions of devices within a PMOS region of the semiconductor device (104) and the CAPOLY layer prevents etching of devices within an NMOS region of the semiconductor device. Subsequently, an epitaxial formation process (106) is performed that forms or deposits epitaxial regions and introduces a first type of strain across the channel regions in the PMOS region. Then, the semiconductor device is annealed (108) to cause the CAPOLY layer to introduce a second type of strain across the channel regions in the NMOS region. After annealing, the CAPOLY layer is removed (110).

    摘要翻译： 本发明通过提供制造方法来促进半导体制造，该方法选择性地将应变应用于器件的沟道区，同时减轻所采用的掩模操作。 在半导体器件（102）的NMOS区域上形成CAPOLY层。 在半导体器件（104）的PMOS区域内的器件的有源区域上执行凹蚀刻，并且CAPOLY层防止在半导体器件的NMOS区域内的器件的蚀刻。 随后，执行形成或沉积外延区域并在PMOS区域中的沟道区域上引入第一类型的应变的外延形成工艺（106）。 然后，半导体器件被退火（108）以使CAPOLY层在NMOS区域中的沟道区域上引入第二类型的应变。 退火后，去除CAPOLY层（110）。

    Body contacted transistor with reduced parasitic capacitance
    7.
    发明授权
    Body contacted transistor with reduced parasitic capacitance 有权

    公开(公告)号：US09269783B2

    公开(公告)日：2016-02-23

    申请号：US13420123

    申请日：2012-03-14

    申请人： Antonio L. P. Rotondaro

    发明人： Antonio L. P. Rotondaro

    IPC分类号： H01L29/423 ,  H01L29/49 ,  H01L29/786

    CPC分类号： H01L29/42384 ,  H01L29/4908 ,  H01L29/78615

    摘要： A body contacted semiconductor-on-insulator (SOI) metal gate containing transistor that has a reduced parasitic gate capacitance is provided in which a metal portion of a gate stack is removed over the body contact region and a silicon-containing material is formed that contacts the gate dielectric in the body contact region of an SOI substrate. This causes an increase of the effective gate dielectric thickness on the body contact region by greater than 5 angstroms (Å). This results in a lower parasitic capacitance at the body contact region.

    Body contacted transistor with reduced parasitic capacitance
    8.
    发明授权
    Body contacted transistor with reduced parasitic capacitance 有权
    体接触晶体管具有降低的寄生电容

    公开(公告)号：US08441071B2

    公开(公告)日：2013-05-14

    申请号：US12652364

    申请日：2010-01-05

    申请人： Antonio L. P. Rotondaro

    发明人： Antonio L. P. Rotondaro

    IPC分类号： H01L27/12

    CPC分类号： H01L29/42384 ,  H01L29/4908 ,  H01L29/78615

    摘要： A body contacted semiconductor-on-insulator (SOI) metal gate containing transistor that has a reduced parasitic gate capacitance is provided in which a metal portion of a gate stack is removed over the body contact region and a silicon-containing material is formed that contacts the gate dielectric in the body contact region of an SOI substrate. This causes an increase of the effective gate dielectric thickness on the body contact region by greater than 5 angstroms (Å). This results in a lower parasitic capacitance at the body contact region.

    摘要翻译： 提供了一种接触绝缘体上半导体（SOI）金属栅极的晶体管，其具有降低的寄生栅极电容，其中栅极堆叠的金属部分在主体接触区域上被去除，并且形成接触的含硅材料 在SOI衬底的体接触区域中的栅极电介质。 这导致在身体接触区域上的有效栅极电介质厚度增加大于5埃（Å）。 这导致在身体接触区域的较低的寄生电容。